MC88915T 데이터 시트보기 (PDF) - Motorola => Freescale

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MC88915T

Low Skew CMOS PLL Clock Drlvers,3-State 55,70,100,133 and 160MHz Versions

Motorola => Freescale 

MC88915TFN133 (continued)

AC CHARACTERISTICS (TA =–40° C to +85° C, VCC = 5.0V ±5%, Load = 50Ω Terminated to VCC/2)

Symbol

Parameter

Min

Max

Unit

Condition

tRISE/FALL

Outputs

tRISE/FALL1

2X_Q Output

tPULSE WIDTH1

(Q0–Q4, Q5, Q/2)

tPULSE WIDTH1

(2X_Q Output)

tPULSE WIDTH1

(2X_Q Output)

Rise/Fall Time, All Outputs

(Between 0.2VCC and 0.8VCC)

Rise/Fall Time Into a 20pF Load, With Ter-

mination Specified in Note 2

Output Pulse Width: Q0, Q1, Q2, Q3, Q4,

Q5, Q/2 @ VCC/2

Output Pulse Width:

2X_Q @ 1.5V

66–133MHz

40–65MHz

Output Pulse Width:

2X_Q @ VCC/2

66–133MHz

40–65MHz

1.0

0.5

0.5tCYCLE – 0.5 2

0.5tCYCLE – 0.5 2

0.5tCYCLE – 0.9

0.5tCYCLE – 0.5 2

0.5tCYCLE – 0.9

2.5

1.6

0.5tCYCLE + 0.5 2

0.5tCYCLE + 0.5 2

0.5tCYCLE + 0.9

0.5tCYCLE + 0.5 2

0.5tCYCLE + 0.9

ns Into a 50Ω Load

Terminated to VCC/2

ns tRISE: 0.8V – 2.0V

tFALL: 2.0V – 0.8V

ns Into a 50Ω Load

Terminated to VCC/2

ns Must Use Termination

Specified in Note 2

ns Into a 50Ω Load

Terminated to VCC/2

tPD 1,3

SYNC Feedback

SYNC Input to Feedback Delay

(Measured at SYNC0 or 1 and

FEEDBACK Input Pins)

(With 1MΩ from RC1 to An VCC)

–1.05

–0.25

(With 1MΩ from RC1 to An GND)

ns See Note 4 and

Figure 2 for Detailed

Explanation

+1.25

+3.25

tSKEWr 1,4

Output–to–Output Skew Between Outputs

—

(Rising) See Note 5 Q0–Q4, Q/2 (Rising Edges Only)

tSKEWf 1,4

(Falling)

Output–to–Output Skew Between Outputs

—

Q0–Q4 (Falling Edges Only)

tSKEWall1,4

Output–to–Output Skew 2X_Q, Q/2,

—

Q0–Q4 Rising, Q5 Falling

tLOCK5

Time Required to Acquire Phase–Lock

1.0

From Time SYNC Input Signal is

Received

500

ps All Outputs Into a

Matched 50Ω Load

Terminated to VCC/2

500

ps All Outputs Into a

Matched 50Ω Load

Terminated to VCC/2

750

ps All Outputs Into a

Matched 50Ω Load

Terminated to VCC/2

10

ms Also Time to LOCK

Indicator High

tPZL6

Output Enable Time OE/RST to 2X_Q,

3.0

Q0–Q4, Q5, and Q/2

14

ns Measured With the

PLL_EN Pin Low

tPHZ,tPLZ6

Output Disable Time OE/RST to 2X_Q,

3.0

Q0–Q4, Q5, and Q/2

14

ns Measured With the

PLL_EN Pin Low

1. These specifications are not tested, they are guaranteed by statistcal characterization. See AC specification Note 1.

2. TCYCLE in this spec is 1/Frequency at which the particular output is running.

3. The TPD specification’s min/max values may shift closer to zero if a larger pullup resistor is used.

4. Under equally loaded conditions and at a fixed temperature and voltage.

5. With VCC fully powered–on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1µF, tLOCK minimum is with

C1 = 0.01µF.

6. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is reached.

MOTOROLA

9

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