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NLV74HC4052ADR2G(2013) 데이터 시트보기 (PDF) - ON Semiconductor

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NLV74HC4052ADR2G
(Rev.:2013)
ON-Semiconductor
ON Semiconductor 
NLV74HC4052ADR2G Datasheet PDF : 17 Pages
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MC74HC4051A, MC74HC4052A, MC74HC4053A
LOGIC DIAGRAM
MC74HC4053A
Triple SinglePole, DoublePosition Plus Common Off
X0 12
X1 13
X SWITCH
14 X
Y0 2
ANALOG
INPUTS/OUTPUTS
Y1 1
Z0 5
Z1 3
A 11
CHANNEL‐SELECT
INPUTS
B 10
C9
ENABLE 6
Y SWITCH
Z SWITCH
15 Y
COMMON
OUTPUTS/INPUTS
4Z
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
NOTE: This device allows independent control of each switch.
ChannelSelect Input A controls the XSwitch, Input B controls
the YSwitch and Input C controls the ZSwitch
FUNCTION TABLE MC74HC4053A
Control Inputs
Enable
Select
CBA
ON Channels
L
L L L Z0 Y0 X0
L
L L H Z0 Y0 X1
L
L H L Z0 Y1 X0
L
L H H Z0 Y1 X1
L
H L L Z1 Y0 X0
L
H L H Z1 Y0 X1
L
H H L Z1 Y1 X0
L
H H H Z1 Y1 X1
H
XXX
NONE
X = Don’t Care
Pinout: MC74HC4053A (Top View)
VCC Y X X1 X0 A B C
16 15 14 13 12 11 10 9
12345678
Y1 Y0 Z1 Z Z0 Enable VEE GND
MAXIMUM RATINGS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VCC Positive DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Referenced to VEE) – 0.5 to + 14.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VEE Negative DC Supply Voltage (Referenced to GND)
– 7.0 to + 5.0
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ VIS AnalogInputVoltage
VEE 0.5 to
V
VCC + 0.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Vin Digital Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5 V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ I
DC Current, Into or Out of Any Pin
± 25
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ PD Power Dissipation in Still Air,
Plastic DIP†
750
mW
EIAJ/SOIC Package†
500
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TSSOP Package†
450
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Tstg Storage Temperature Range
– 65 to + 150
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TL Lead Temperature, 1 mm from Case for 10 Seconds
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Plastic DIP, SOIC or TSSOP Package
260
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
EIAJ/SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
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