MC56F8346MFV60 데이터 시트보기 (PDF) - Motorola => Freescale
부품명
상세내역
제조사
MC56F8346MFV60 Datasheet PDF : 160 Pages
| |||
Freescale Semiconductor, Inc.
Table 2-2 56F8346 Signal and Package Information for the 144 Pin LQFP
Signal Name Pin No. Type
PS
(CS0)
46
Output
State
During
Reset
Tri-stated
Signal Description
Program Memory Select — This signal is actually CS0 in
the EMI, which is programmed at reset for compatibility
with the 56F80x PS signal. PS is asserted low for external
program memory access.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), PS is tri-stated when the external
bus is inactive.
(GPIOD8)
Input/
Output
Input
Port D GPIO — This GPIO pin can be individually
programmed as an input or output pin.
CS0 resets to provide the PS function as defined on the
56F80x devices.
DS
(CS1)
To deactivate the internal pull-up resistor, clear bit 8 in the
GPIOD_PUR register.
47
Output Tri-stated Data Memory Select — This signal is actually CS1 in the
EMI, which is programmed at reset for compatibility with
the 56F80x DS signal. DS is asserted low for external data
memory access.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), DS is tri-stated when the external
bus is inactive.
(GPIOD9)
Input/
Output
Input
Port D GPIO — This GPIO pin can be individually
programmed as an input or output pin.
CS1 resets to provide the DS function as defined on the
56F80x devices.
GPIOD0
48
Input/
Output
Input
To deactivate the internal pull-up resistor, clear bit 9 in the
GPIOD_PUR register.
Port D GPIO — These two GPIO pins can be individually
programmed as input or output pins.
(CS2)
GPIOD1
(CS3)
Output Tri-stated Chip Select — CS2 - CS3 may be programmed within the
49
EMI module to act as chip selects for specific areas of the
external memory map.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), CS2 - CS3 are tri-stated when the
external bus is inactive.
At reset, these pins are configured as GPIO.
To deactivate the internal pull-up resistor, clear the
appropriate GPIO bit in the GPIOD_PUR register.
Example: GPIOD0, clear bit 0 in the GPIOD_PUR register.
20
56F8346 Technical Data
For More Information On This Product,
Go to: www.freescale.com
Preliminary
Share Link: 