MOST SIGNIFICANT
DIGIT
1A
0B
OUT
0
1
C
D
1
CLOCK
Eout
CASC
Ein
“9”
ST
CLEAR S
LEAST SIGNIFICANT
DIGIT
0A
0B
OUT
1
0
C
D
2
CLOCK
Eout
CASC
Ein
“9”
ST
CLEAR S
NOTE: More than two MC14527Bs
may be cascaded using this
configuration.
CLOCK
0 1 2 34 5 6 7 8 90 1 2 34 5 6 7 8 90
CLOCK
OUT
DRM 2
One of four output pulses contributed by DRM 2 to
output for every 100 clock pulses in for preset No. of 94.
Figure 4. Two MC14527Bs in Cascade with Preset No. of 94
MC14527B
6
MOTOROLA CMOS LOGIC DATA