THRESHOLD
+3 V
DETECTOR
1 REFout
REFin 20
INTEGRATOR
2 LD
Din 19
3 φR
CLK 18
MCU
4 φV
ENB 17
+3V
LOW–PASS
FILTER
5 VPD
6 PDout
7
GND
OUTPUT A 16
15
OUTPUT B
VDD 14
GENERAL–PURPOSE
DIGITAL OUTPUT
+3 V
8
Rx
9
NC TEST 1
TEST 2 13 NC
VCC 12
Q1
NOTE 2
10 fin
fin 11
1000 pF
UHF
VCO
BUFFER
UHF OUTPUT
NOTES:
1. When used, the φR and φV outputs are fed to an external combiner/loop filter. See the Phase–
Locked Loop — Low–Pass Filter Design page for additional information.
2. Transistor Q1 is required only if the standby feature is needed. Q1 permits the bipolar section
of the device to be shut down via use of the general–purpose digital pin, OUTPUT B. If the stand-
by feature is not needed, tie Pin 12 directly to the power supply.
3. For optimum performance, bypass the VCC, VDD, and VPD pins to GND with low–inductance ca-
pacitors.
4. The R counter is programmed for a divide value = REFin / fR. Typically, fR is the tuning resolution
required for the VCO. Also, the VCO frequency divided by fR = NT = N x 64 + A; this determines
the values (N, A) that must be programmed into the N and A counters, respectively.
Figure 21. Example Application
DEVICE #1
OUTPUT A
Din
CLK ENB (DATA OUT)
DEVICE #2
OUTPUT A
Din
CLK ENB (DATA OUT)
CMOS
MCU
OPTIONAL
NOTE: See related Figures 23, 24, and 25.
Figure 22. Cascading Two Devices
MC145202
20
MOTOROLA