MC145202 데이터 시트보기 (PDF) - Motorola => Freescale

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MC145202

Low-Voltage 2.0 GHz PLL Frequency Synthesizer Includes On-Board 64/65 Prescaler

Motorola => Freescale 

ENB

NOTE NOTE

CLK

1

23

45

6

7

8

9

10 11 12 13 14 15 16 4

5

MSB

LSB

Din

R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0

0 CRYSTAL MODE, SHUT DOWN

1 CRYSTAL MODE, ACTIVE

2 REFERENCE MODE, REFin ENABLED and REFout

STATIC LOW

3 REFERENCE MODE, REFout = REFin (BUFFERED)

4 REFERENCE MODE, REFout = REFin/2

5 REFERENCE MODE, REFout = REFin/4

6 REFERENCE MODE, REFout = REFin/8 (NOTE 3)

7 REFERENCE MODE, REFout = REFin/16

OCTAL VALUE

0 0 0 0 NOT ALLOWED

0 0 0 1 R COUNTER = ÷ 1 (NOTE 6)

0 0 0 2 NOT ALLOWED

0 0 0 3 NOT ALLOWED

0 0 0 4 NOT ALLOWED

0 0 0 5 R COUNTER = ÷ 5

0 0 0 6 R COUNTER = ÷ 6

0 0 0 7 R COUNTER = ÷ 7

0 0 0 8 R COUNTER = ÷ 8

· · ··

· · ··

· · ··

1 F F E R COUNTER = ÷ 8190

1 F F F R COUNTER = ÷ 8191

BINARY VALUE

HEXADECIMAL VALUE

NOTES:

1. Bits R15 through R13 control the configurable “OSC or 4–stage divider” block (see Block Diagram).

2. Bits R12 through R0 control the “13–stage R counter” block (see Block Diagram).

3. A power–on initialize circuit forces a default REFin to REFout ratio of eight.

4. At this point, bits R13, R14, and R15 are stored and sent to the “OSC or 4–Stage Divider” block in the Block Diagram. Bits R0 – R12

are loaded into the first buffer in the double–buffered section of the R register. Therefore, the R counter divide ratio is not altered yet

and retains the previous ratio loaded. The C and A registers are not affected.

5. Optional load pulse. At this point, bits R0 – R12 are transferred to the second buffer of the R register. The R counter begins dividing

by the new ratio after completing the rest of the present count cycle. CLK must be low during the ENB pulse, as shown. The C and A

registers are not affected. The first buffer of the R register is not affected. Also, see note 3 of Figure 15 for an alternate method of loading

the second buffer in the R register.

6. Allows direct access to reference input of phase/frequency detectors.

Figure 16. R Register Access and Format (16 Clock Cycles are Used)

MOTOROLA

MC145202

15

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