MAX3799(2009) 데이터 시트보기 (PDF) - Maxim Integrated

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MAX3799
(Rev.:2009)

1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver

Maxim Integrated 

1Gbps to 14Gbps, SFP+ Multirate Limiting

Amplifier and VCSEL Driver

Table 3. Circuit Response to Single-Point Faults (continued)

PIN

NAME

SHORT TO VCC

SHORT TO GND

OPEN

30

VCCR Normal

Disabled—Fault (external supply

shorted) (Note 2)

Normal (Note 3)—Redundant path

31

CAZ2 Normal (Note 1)

Normal (Note 1)

Normal (Note 1)

32

CAZ1

(VEER)

Disabled—Fault (external supply

shorted) (Note 2)

Normal (Note 3)—Redundant path Normal (Note 3)—Redundant path

Note 1: Normal—Does not affect laser power.

Note 2: Supply-shorted current is assumed to be primarily on the circuit board (outside this device) and the main supply is

collapsed by the short.

Note 3: Normal in functionality, but performance could be affected.

Warning: Shorted to VCC or shorted to ground on some pins can violate the Absolute Maximum Ratings.

3-Wire Digital Communication

The MAX3799 implements a proprietary 3-wire digital

interface. An external controller generates the clock. The

3-wire interface consists of an SDA bidirectional data

line, an SCL clock signal input, and a CSEL chip-select

input (active high). The external master initiates a data

transfer by asserting the CSEL pin. The master starts to

generate a clock signal after the CSEL pin has been set

to 1. All data transfers are most significant bit (MSB) first.

Protocol

Each operation consists of 16-bit transfers (15-bit

address/data, 1-bit RWN). The bus master generates

16 clock cycles to SCL. All operations transfer 8 bits to

the MAX3799. The RWN bit determines if the cycle is

read or write. See Table 4.

Register Addresses

The MAX3799 contains 17 registers available for pro-

gramming. Table 5 shows the registers and addresses.

Write Mode (RWN = 0)

The master generates 16 clock cycles at SCL in total.

The master outputs a total of 16 bits (MSB first) to the

SDA line at the falling edge of the clock. The master

closes the transmission by setting CSEL to 0. Figure 4

shows the interface timing.

Read Mode (RWN = 1)

The master generates 16 clock cycles at SCL in total.

The master outputs a total of 8 bits (MSB first) to the

SDA line at the falling edge of the clock. The SDA line is

released after the RWN bit has been transmitted. The

slave outputs 8 bits of data (MSB first) at the rising edge

of the clock. The master closes the transmission by set-

ting CSEL to 0. Figure 4 shows the interface timing.

Mode Control

Normal mode allows read-only instruction for all regis-

ters except MODINC and BIASINC. The MODINC and

BIASINC registers can be updated during normal

mode. Doing so speeds up the laser control update

through the 3-wire interface by a factor of two. The nor-

mal mode is the default mode.

Setup mode allows the master to write unrestricted data

into any register except the status (TXSTAT1, TXSTAT2,

and RXSTAT) registers. To enter the setup mode, the

MODECTRL register (address = H0x0E) must be set to

H0x12. After the MODECTRL register has been set to

H0x12, the next operation is unrestricted. The setup

mode is automatically exited after the next operation is

finished. This sequence must be repeated if further

unrestricted settings are necessary.

Table 4. Digital Communication Word Structure

BIT

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Register Address

RWN

Data that is written or read.

20 ______________________________________________________________________________________

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