MAX1535A 데이터 시트보기 (PDF) - Maxim Integrated
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MAX1535A Datasheet PDF : 39 Pages
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Highly Integrated Level 2 SMBus
Battery Charger
A
B
C
D
EF
G
tLOW tHIGH
SMBCLK
SMBDATA
tSU:STA tHD:STA
tSU:DAT tHD:DAT
tHD:DAT
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE
H = LSB OF DATA CLOCKED INTO SLAVE
I = SLAVE PULLS SMBDATA LINE LOW
Figure 4. SMBus Write Timing
H
IJ
K
LM
tSU:STO tBUF
J = ACKNOWLEDGE CLOCKED INTO MASTER
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION, DATA EXECUTED BY SLAVE
M = NEW START CONDITION
A
B
C
D
EF
G
tLOW tHIGH
SMBCLK
H
I
J
K
SMBDATA
tSU:STA tHD:STA
tSU:DAT
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
tHD:DAT
E = SLAVE PULLS SMBDATA LINE LOW
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO MASTER
H = LSB OF DATA CLOCKED INTO MASTER
tSU:DAT
tSU:STO tBUF
I = ACKNOWLEDGE CLOCK PULSE
J = STOP CONDITION
K = NEW START CONDITION
Figure 5. SMBus Read Timing
tery being charged, as well as with any host system
that monitors the battery-to-charger communications as
a level 2 SMBus charger. The MAX1535A is an SMBus
slave device and does not initiate communication on
the bus. It responds to the 7-bit address 0b0001001. In
addition, the MAX1535A has two identification (ID) reg-
isters: a 16-bit device ID register (0x0006), and a 16-bit
manufacturer ID register (0x004D).
The data input SDA and clock input SCL pins have
Schmitt-trigger inputs that can accommodate slow
edges; however, the rising and falling edges should still
be faster than 1µs and 300ns, respectively.
Communication starts with the master signaling the
beginning of a transmission with a START condition,
which is a high-to-low transition on SDA, while SCL is
high. When the master has finished communicating
with the slave, the master issues a STOP condition,
which is a low-to-high transition on SDA, while SCL is
high. The bus is then free for another transmission.
Figures 4 and 5 show the timing diagram for signals on
the SMBus interface. The address byte, command
byte, and data byte are transmitted between the START
and STOP conditions. The SDA state is allowed to
change only while SCL is low, except for the START
18 ______________________________________________________________________________________
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