MAX104 데이터 시트보기 (PDF) - Maxim Integrated

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MAX104

±5V, 1Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier

Maxim Integrated 

±5V, 1Gsps, 8-Bit ADC with

On-Chip 2.2GHz Track/Hold Amplifier

-10dBm (100mV clock signal amplitude) to +10dBm

(1V clock signal amplitude). The MAX104 dynamic per-

formance specifications are determined by a single-

ended clock drive of +4dBm (500mV clock signal

amplitude). To avoid saturation of the input amplifier

stage, limit the clock power level to a maximum of

+10dBm.

Differential Clock Inputs (Sine-Wave Drive)

The advantages of differential clock drive (Figure 13b,

Table 5) can be obtained by using an appropriate

balun or transformer to convert single-ended sine-wave

sources into differential drives. The precision on-chip,

laser-trimmed 50Ω clock-termination resistors ensure

excellent amplitude matching. Refer to Single-Ended

Clock Inputs (Sine-Wave Drive) for proper input ampli-

tude requirements.

Single-Ended Clock Inputs (ECL Drive)

Configure the MAX104 for single-ended ECL clock drive

by connecting the clock inputs as shown in Figure 13c

(Table 5). A well bypassed VBB supply (-1.3V) is essen-

tial to avoid coupling noise into the undriven clock input,

which would degrade dynamic performance.

Differential Clock Inputs (ECL Drive)

The MAX104 may be driven from a standard differential

(Figure 13d, Table 5) ECL clock source by setting the

clock termination voltage at CLKCOM to -2V. Bypass

the clock-termination return (CLKCOM) as close as

possible to the ADC with a 0.01µF capacitor connected

to GNDI.

AC-Coupling Clock Inputs

The clock inputs CLK+ and CLK- can also be driven

with positive referenced ECL (PECL) logic if the clock

+0.5V

CLK+

CLK- = 0V

-0.5V

t

NOTE: CLKCOM = 0V

Figure 13a. Single-Ended Clock Input Signals

+0.5V

CLK+

CLK-

-0.5V

t

NOTE: CLKCOM = 0V

Figure 13b. Differential Clock Input Signals

CLK+

-0.8V

CLK- = -1.3V

CLK+

-0.8V

CLK-

-1.8V

t

-1.8V

t

NOTE: CLKCOM = -2V

NOTE: CLKCOM = -2V

Figure 13c. Single-Ended ECL Clock Drive

Figure 13d. Differential ECL Clock Drive

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