M38022E7-XXXFP 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC

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M38022E7-XXXFP

8-BIT SINGLE-CHIP MICROCOMPUTER

MITSUBISHI ELECTRIC  

HARDWARE

FUNCTIONAL DESCRIPTION

I/O Ports

Direction registers

The 3802 group has 56 programmable I/O pins arranged in seven

I/O ports (ports P0 to P6). The I/O ports have direction registers

which determine the input/output direction of each individual pin.

Each bit in a direction register corresponds to one pin, each pin

can be set to be input port or output port.

When “0” is written to the bit corresponding to a pin, that pin be-

comes an input pin. When “1” is written to that bit, that pin be-

comes an output pin.

If data is read from a pin which is set to output, the value of the

port output latch is read, not the value of the pin itself. Pins set to

input are floating. If a pin set to input is written to, only the port

output latch is written to and the pin remains floating.

Table 6. list of I/O port functions

Pin

Name

Input/Output

I/O Format

Non-Port Function

Related SFRs

Ref.No.

P00–P07

Port P0

Input/output,

individual bits

CMOS 3-state output

CMOS compatible

input level

Address low-order byte

output

CPU mode register

CMOS 3-state output

Input/output,

Address high-order

P10–P17

Port P1

CMOS compatible

CPU mode register

(1)

individual bits

byte output

input level

P20–P27

P30/DA1

P31/DA2

P32–P37

P40/INT4,

P41/INT0,

P43/INT2

P44/RXD,

P45/TXD,

P46/SCLK1,

P47/SRDY1

P50/SIN2,

P51/SOUT2,

P52/SCLK2,

P53/SRDY2

P54/CNTR0,

P55/CNTR1

P56/PWM

P57/INT3

P60/AN0–

P67/AN7

Port P2

Port P3

Port P4

Port P5

Port P6

Input/output,

individual bits

CMOS 3-state output

CMOS compatible

input level

Data bus I/O

CPU mode register

CMOS 3-state output D-A conversion output AD/DA control register

Input/output,

(2)

CMOS compatible

CPU mode register

individual bits

input level

Control signal I/O

CPU mode register

(1)

Interrupt edge selection

External interrupt input register

(3)

CMOS 3-state output

Input/output,

CMOS compatible

(4)

individual bits

Serial I/O1 control

input level

(5)

Serial I/O1 function I/O register

(6)

UART control register

(7)

(8)

Serial I/O2 control

(9)

Serial I/O2 function I/O

register

(10)

CMOS 3-state output

Input/output,

(11)

CMOS compatible

individual bits

Timer X and Timer Y

input level

Timer XY mode register (12)

function I/O

PWM output

PWM control register

(13)

External interrupt input Interrupt edge selection register (3)

CMOS 3-state output

Input/output,

CMOS compatible

A-D conversion input

(14)

individual bits

input level

Note 1: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as func-

tion I/O ports, refer to the applicable sections.

2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.

When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.

3802 GROUP USER’S MANUAL

1-15

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