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HM5257165BTD-75 데이터 시트보기 (PDF) - Elpida Memory, Inc
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HM5257165BTD-75
512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword × 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM
Elpida Memory, Inc
HM5257165BTD-75 Datasheet PDF : 62 Pages
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HM5257165B/HM5257805B/HM5257405B-75/A6
Block Diagram
(HM5257805B)
Column address
counter
A0 to A12, BA0, BA1
Upper pellet
A0 to A9, A11
Column address
buffer
A0 to A12, BA0, BA1
Row address
buffer
Refresh
counter
Row decoder
Memory array
Bank0
8192 row
×
2048 column
×
4 bit
Row decoder
Memory array
Bank1
8192 row
×
2048 column
×
4 bit
Row decoder
Memory array
Bank2
8192 row
×
2048 column
×
4 bit
Row decoder
Memory array
Bank3
8192 row
×
2048 column
×
4 bit
Input buffer Output buffer
DQ4 to DQ7
DQ0 to DQ3
Input buffer Output buffer
CLK
CKE
CS
RAS
CAS
WE
DQM
Memory array
Bank0
8192 row
×
2048 column
×
4 bit
Row decoder
Column address
counter
Memory array
Bank1
8192 row
×
2048 column
×
4 bit
Row decoder
Memory array
Bank2
8192 row
×
2048 column
×
4 bit
Row decoder
Memory array
Bank3
8192 row
×
2048 column
×
4 bit
Row decoder
Column address
buffer
Row address
buffer
Refresh
counter
Lower pellet
Data Sheet E0081H10
7
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