M150X3-T05 데이터 시트보기 (PDF) - Unspecified

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M150X3-T05

15.0” TFT Liquid Crystal Display module with 4 CCFL Backlight units and 60 pins TTL interface

Unspecified 

Issued Date:Mar.01’2002

Model No.: M150X3-T05

Approval

6. INTERFACE TIMING

6.1 INPUT SIGNAL TIMING SPECIFICATIONS

The input signal timing specifications are shown as the following table and timing diagram.

Signal Parameter

DCLK Pixel clock Frequency

Symbol Min Typ Max Unit

Fck

- 32.5 40 MHz

Pixel clock period

Tck

25 30 40 ns

Duty ratio (%Tch)

-

45

50

55

%

High time

Low time

DATA Setup time

Hold time

DE Setup time

Hold time

Vertical Vertical Frequency

Signal Vertical display active period

Vertical display blank period

Vertical period

Horizontal Horizontal display active

Signal period

Horizontal display blank period

Horizontal period

Tckh

Tckl

Tsd

Thd

Tsde

Thde

Fv

Tvda

Tvdb

Tvp

Thda

Thdb

Thp

5

-

-

ns

5

-

-

ns

4

-

-

ns

4

-

-

ns

4

-

-

ns

4

-

-

ns

-

60 75 Hz

768 768 768 Thp

1

38

-

Thp

769 806

-

Thp

512 512 512 Tck

38 160 388 Tck

550 672 900 Tck

Remarks

Tch/Tck

Note (1) Because this module is operated by DE only mode, Hsync and Vsync input signals should be set

to low logic level or ground. Otherwise, this module would operate abnormally.

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Version 2.1

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