LTC6990I 데이터 시트보기 (PDF) - Linear Technology
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LTC6990I Datasheet PDF : 30 Pages
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LTC6990
APPLICATIONS INFORMATION
Additionally, by choosing the VCO’s specifications
shrewdly, the frequency error (in percent) due to VSET
variation is reduced to ΔVSET/VSET = ±3%. To realize this
improvement, the design must abide by three conditions.
First, the VIN voltage must be positive throughout the
range. Second, choose VMAX/VMIN ≥ fMAX / fMIN. Last,
choose RVCO/RSET ≥ R4/R3.
Figure 13 shows a design similar to the previous design
example where the VMIN voltage is now specified to be
0.4V. This satisfies the VMAX/VMIN ≥ fMAX /fMIN condition
and the design assures that the output frequency error
due to VSET variation is only ±3%.
Eliminating VSET Error Effects with DAC Frequency
Control
Many DACs allow for the use of an external reference.
If such a DAC is used to provide the VCTRL voltage, the
VSET error is eliminated by buffering VSET and using it as
the DAC’s reference voltage, as shown in Figure 14. The
DAC’s output voltage now tracks any VSET variation and
eliminates it as an error source. The SET pin cannot be
tied directly to the reference input of the DAC because
the current drawn by the DAC’s REF input would affect
the frequency.
ISET Extremes (Master Oscillator Frequency Extremes)
Pushing ISET outside of the recommended 1.25µA to 20µA
range forces the master oscillator to operate outside of the
62.5kHz to 1MHz range in which it is most accurate. The
oscillator will still function with reduced accuracy in its
extended range (see the Electrical Characteristics section).
The LTC6990 is designed to function normally for ISET
as low as 1.25µA. At approximately 500nA, the oscillator
output will be frozen in its current state. For NDIV = 1 or 2,
OUT will halt in a low state. But for larger divider ratios,
it could halt in a high or low state. This avoids introduc-
ing short pulses while modulating a very low frequency
output. Note that the output will not be disabled as when
OE is low (e.g. the output will not enter a high impedance
state if Hi-Z = 1).
At the other extreme, the master oscillator frequency can
reach 2MHz for ISET = 40μA (RSET = 25k). It is not recom-
mended to operate the master oscillator beyond 2MHz
because the accuracy of the DIV pin ADC will suffer.
V+
1/2
LTC6078
OE
OUT
LTC6990
GND
V+
SET
DIV
6990 F14
V+
C1
0.1µF R1
R2
V+
DIN VCC
REF
RVCO
µP
CLK LTC1659 VOUT
fOUT
= 1MHz • 50kΩ
NDIV • RVCO
•
1+
RVCO
RSET
−
DIN
4096
DIN = 0 to 4095
CS/LD
GND
RSET
Figure 14. Digitally Controlled Oscillator with VSET Variation Eliminated
For more information www.linear.com/LTC6990
6990fc
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