LTC2230 데이터 시트보기 (PDF) - Linear Technology

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LTC2230

10-Bit,170Msps/ 135Msps ADCs

Linear Technology 

LTC2230/LTC2231

APPLICATIO S I FOR ATIO

60) may be used to provide the common mode bias level.

VCM can be tied directly to the center tap of a transformer

to set the DC input level or as a reference level to an op amp

differential driver circuit. The VCM pin must be bypassed to

ground close to the ADC with a 2.2μF or greater capacitor.

Input Drive Impedance

As with all high performance, high speed ADCs, the

dynamic performance of the LTC2230/LTC2231 can be

influenced by the input drive circuitry, particularly the

second and third harmonics. Source impedance and input

reactance can influence SFDR. At the falling edge of ENC,

the sample-and-hold circuit will connect the 1.6pF sam-

pling capacitor to the input pin and start the sampling

period. The sampling period ends when ENC rises, holding

the sampled input on the sampling capacitor. Ideally the

input circuitry should be fast enough to fully charge

the sampling capacitor during the sampling period

1/(2FENCODE); however, this is not always possible and the

incomplete settling may degrade the SFDR. The sampling

glitch has been designed to be as linear as possible to

minimize the effects of incomplete settling.

For the best performance, it is recommended to have a

source impedance of 100Ω or less for each input. The

source impedance should be matched for the differential

inputs. Poor matching will result in higher even order

harmonics, especially the second.

Input Drive Circuits

Figure 3 shows the LTC2230/LTC2231 being driven by an

RF transformer with a center tapped secondary. The

secondary center tap is DC biased with VCM, setting the

ADC input signal at its optimum DC level. Terminating on

the transformer secondary is desirable, as this provides a

common mode path for charging glitches caused by the

sample and hold. Figure 3 shows a 1:1 turns ratio trans-

former. Other turns ratios can be used if the source

impedance seen by the ADC does not exceed 100Ω for

each ADC input. A disadvantage of using a transformer is

the loss of low frequency response. Most small RF trans-

formers have poor performance at frequencies below

1MHz.

Figure 4 demonstrates the use of a differential amplifier to

20

convert a single ended input signal into a differential input

signal. The advantage of this method is that it provides low

frequency input response; however, the limited gain band-

width of most op amps will limit the SFDR at high input

frequencies.

Figure 5 shows a single-ended input circuit. The imped-

ance seen by the analog inputs should be matched. This

circuit is not recommended if low distortion is required.

The 25Ω resistors and 12pF capacitor on the analog inputs

serve two purposes: isolating the drive circuitry from the

sample-and-hold charging glitches and limiting the

wideband noise at the converter input. For input frequen-

cies higher than 100MHz, the capacitor may need to be

decreased to prevent excessive signal loss.

0.1μF T1

ANALOG

1:1

INPUT

25Ω

25Ω 0.1μF

25Ω 25Ω

T1 = MA/COM ETC1-1T

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

VCM

2.2μF

AIN+

AIN+

12pF

AIN–

AIN–

LTC2230/

LTC2231

22301 F03

Figure 3. Single-Ended to Differential

Conversion Using a Transformer

HIGH SPEED

DIFFERENTIAL

AMPLIFIER

25Ω

ANALOG

INPUT

++

3pF

CM

– – 25Ω

AMPLIFIER = LTC6600-20, AD8138, ETC.

VCM

2.2μF

AIN+

AIN+

12pF

AIN–

AIN–

3pF

LTC2230/

LTC2231

22301 F04

Figure 4. Differential Drive with an Amplifier

1k 1k

0.1μF

ANALOG

INPUT

25Ω

25Ω

0.1μF

VCM

2.2μF

AIN+

AIN+

12pF AIN–

AIN–

LTC2230/

LTC2231

22301 F05

Figure 5. Single-Ended Drive

22301fb

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