LTC1702A 데이터 시트보기 (PDF) - Linear Technology

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LTC1702A

Dual 550kHz Synchronous 2-Phase Switching Regulator Controller

Linear Technology 

LTC1702A

APPLICATIONS INFORMATION

remains in this state until both RUN/SS pins are pulled low

simultaneously, the power supply is recycled, or the

FAULT pin is pulled low externally. This behavior is in-

tended to protect a potentially expensive load from over-

voltage damage at all costs. Under some conditions, this

behavior can cause the output voltage to undershoot

below ground. If latched FAULT mode is used, a Schottky

diode should be added with its cathode at the output and

its anode at ground to clamp the negative voltage to a safe

level and prevent possible damage to the load and the

output capacitors.

In some circuits, the OV latch can be a liability. Consider

a circuit where the output voltage at one channel may be

changed on the fly by switching in different feedback

resistors. A downward adjustment of greater than 15%

will fire the fault latch, disabling both sides of the LTC1702A

until the power is recycled. In circuits such as this, the fault

latch can be disabled by grounding the FAULT pin. The

internal latch will still be set the first time the output

exceeds +15%, but the 10µA current source pull-up will

not be able to pull FAULT high, and the LTC1702A will

ignore the latch and continue normal operation. FAULT

can also be pulled down with external open-collector logic

to restart a fault-latched LTC1702A as an alternative to

recycling the power. Note that this will not reset the

internal latch; if the external pull-down is released, the

LTC1702A will reenter FAULT mode. To reset the latch,

pull both RUN/SS pins low simultaneously or cycle the

input power.

EXTERNAL COMPONENT SELECTION

POWER MOSFETs

Getting peak efficiency out of the LTC1702A depends

strongly on the external MOSFETs used. The LTC1702A

requires at least two external MOSFETs per side—more if

one or more of the MOSFETs are paralleled to lower on-

resistance. To work efficiently, these MOSFETs must

exhibit low RDS(ON) at 5V VGS (3.3V VGS if the PVCC input

supply is 3.3V) to minimize resistive power loss while they

are conducting current. They must also have low gate

charge to minimize transition losses during switching. On

the other hand, voltage breakdown requirements in a

typical LTC1702A circuit are pretty tame: the 7V maximum

input voltage limits the VDS and VGS the MOSFETs can see

to safe levels for most devices.

Low RDS(ON)

RDS(ON) calculations are pretty straightforward. RDS(ON) is

the resistance from the drain to the source of the MOSFET

when the gate is fully on. Many MOSFETs have RDS(ON)

specified at 4.5V gate drive—this is the right number to

use in LTC1702A circuits running from a 5V supply. As

current flows through this resistance while the MOSFET is

on, it generates I2R watts of heat, where I is the current

flowing (usually equal to the output current) and R is the

MOSFET RDS(ON). This heat is only generated when the

MOSFET is on. When it is off, the current is zero and the

power lost is also zero (and the other MOSFET is busy

losing power).

This lost power does two things: it subtracts from the

power available at the output, costing efficiency, and it

makes the MOSFET hotter—both bad things. The effect is

worst at maximum load when the current in the MOSFETs

and thus the power lost are at a maximum. Lowering

RDS(ON) improves heavy load efficiency at the expense of

additional gate charge (usually) and more cost (usually).

Proper choice of MOSFET RDS(ON) becomes a trade-off

between tolerable efficiency loss, power dissipation and

cost. Note that while the lost power has a significant effect

on system efficiency, it only adds up to a watt or two in a

typical LTC1702A circuit, allowing the use of small, sur-

face mount MOSFETs without heat sinks.

Gate Charge

Gate charge is amount of charge (essentially, the number

of electrons) that the LTC1702A needs to put into the gate

of an external MOSFET to turn it on. The easiest way to

visualize gate charge is to think of it as a capacitance from

the gate pin of the MOSFET to SW (for QT) or to PGND (for

QB). This capacitance is composed of MOSFET channel

charge, actual parasitic drain-source capacitance and Miller-

multiplied gate-drain capacitance, but can be approximated

as a single capacitance from gate to source. Regardless of

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