LT3596IUHG 데이터 시트보기 (PDF) - Linear Technology
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LT3596IUHG Datasheet PDF : 22 Pages
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LT3596
Applications Information
The maximum output voltage must be set to exceed the
maximum LED drop plus 1.07V by a margin greater than
15%. However, this margin must not exceed a value of
10V. This ensures proper adaptive loop control. The equa-
tion below is used to estimate the resistor divider ratio.
The sum of the resistors should be approximately 100k
to avoid noise coupling to the FB pin.
( ) VOUT(MAX) = 1.15 •
VLED(MAX) + 1.07V
=
1.21V
•
1+
R2
R1
VOUT(MAX) = VLED(MAX) + 1.07V + VMARGIN
VMARGIN ≤ 10V
Minimum Input Voltage
The minimum input voltage required to generate an output
voltage is limited by the maximum duty cycle and the
output voltage (VOUT) set by the FB resistor divider. The
duty cycle is:
DC
=
VIN
VD + VOUT
– VCESAT +
VD
where VD is the Schottky forward drop and VCESAT is the
saturation voltage of the internal switch. The minimum
input voltage is:
VIN(MIN)
=
VD
+ VOUT(MAX)
DCMAX
+
VCESAT
–
VD
where VOUT(MAX) is calculated from the equation in the
Adaptive Loop Control section, and DCMAX is the minimum
rating of the maximum duty cycle.
Start-Up
At start-up, when VOUT reaches 90% of the FB programmed
output voltage, the adaptive loop is enabled. At this point,
the LED string with the highest voltage drop is selected. The
output voltage reduces until the selected string’s LED pin
is about 1V. This regulation method ensures that all three
LED strings run their programmed current at a minimum
output voltage despite mismatches in LED forward volt-
age. This minimizes the drop across the internal current
sources and maximizes system efficiency.
Another benefit of this regulation method is that the LT3596
starts up with 10,000:1 dimming even if the PWMn pulse
16
width is 1µs. Since VOUT starts up even if PWMn is low,
the part achieves high dimming ratios with narrow pulse
widths within a couple of PWMn clock cycles.
High Temperature Considerations
The LT3596 provides three channels for LED strings with
internal NPN devices serving as constant current sources.
When LED strings are regulated, the lowest LED pin voltage
is typically 1V. For 100mA of LED current with a 100%
PWM dimming ratio, at least 300mW is dissipated within
the IC due to current sources. If the forward voltages
of the three LED strings are very dissimilar, significant
power dissipation will occur. Thermal calculations must
include the power dissipation in the current sources in
addition to conventional switch DC loss, switch transient
loss and input quiescent loss. For best efficiency, it is
recommended that each LED string have approximately
the same voltage drop.
In addition, the die temperature of the LT3596 must be
lower than the maximum rating of 125°C. This is generally
not a concern unless the ambient temperature is above
100°C. Care should be taken in the board layout to ensure
good heat sinking of the LT3596. The maximum load cur-
rent (300mA) must be derated as the ambient temperature
approaches 125°C. The die temperature is calculated by
multiplying the LT3596 power dissipation by the thermal
resistance from junction to ambient. Power dissipation
within the LT3596 is estimated by calculating the total
power loss from an efficiency measurement and subtract-
ing the losses of the catch diode and the inductor. Thermal
resistance depends on the layout of the circuit board, but
32°C/W is typical for the 5mm × 8mm QFN package.
Board Layout
As with all switching regulators, careful attention must
be paid to the PCB layout and component placement. To
prevent electromagnetic interference (EMI) problems,
proper layout of high frequency switching paths is essential.
Minimize the length and area of all traces connected to the
switching node (SW). Always use a ground plane under
the switching regulator to minimize interplane coupling.
Resistors connected between ground and the CTRL1-3,
CTRLM, FB, TSET, ISETn , RT and EN/UVLO pins are best
connected to a quiet ground.
3596fa
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