L9942 데이터 시트보기 (PDF) - STMicroelectronics
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L9942 Datasheet PDF : 40 Pages
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Functional description of the logic with SPI
L9942
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected ICs is
recommended.
4.6
Serial data out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from
high impedance to a low or high level depending on the status bit 0 (fault condition). The first
rising edge of the CLK input after a high to low transition of the CSN pin will transfer the
content of the selected status register into the data out shift register. Each subsequent
falling edge of the CLK will shift the next bit out.
4.7
Serial clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input
(DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the
falling edge of the CLK signal.
4.8
Data register
The device has eight data registers. The first three bits (bit 0 ... bit 2) at the DI-input are used
to select one of the input registers. All bits are first shifted into an input shift register. After
the rising edge of CSN the contents of the input shift register will be written to the selected
Input Data Register only if a frame of exact 16 data bits are detected. The selected register
will be transferred to DO during the current communication frame.
Figure 9. SPI and registers
DI
CLK
DO
D
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 A0 A1 A2
CSN
INT_2MHz
POR
SPI-
Controll
CLK_ADR
SEL_ERROR
SPI2REG
D A0
A1 A2
Phase Counter
Decay Mode
Slew Rate Step Mode
Register 0 P4 P3 P2 P1 P0 DM2 DM1 DM0 SR1 SR0 ST1 ST0 DIR
Read Only
DAC_Scale
DAC Phase B
DAC Phase A
Register 1 DC2 DC1 DC0 BI4 BI3 BI2 BI1 BI0 AI4 AI3 AI2 AI1 AI0
Current Profile 1
OV Test only
Current Profile 0
Register 2 I4
I3
I2
I1
I0 OVW T 1 T 0
I4
I3
I2
I1
I0
Current Profile 3
PWM Counter PWM
Current Profile 2
Register 3 I4
I3
I2
I1
I0
D1 D0 NPWM I4
I3
I2
I1
I0
Current Profile 5
PWM Counter
Current Profile 4
Register 4 I4
I3
I2
I1
I0
D4 D3 D2 I4
I3
I2
I1
I0
Register 5 I4
Current Profile 7
I3
I2
I1
I0
PWM Counter
Current Profile 6
D7 D6 D5 I4
I3
I2
I1
I0
Read-Only
Register 6 CLR6 SST
PWM
RREF Openload
FT
Freq
ST
Error Phase Phase
B
A
I4
Current Profile 8
I3
I2
I1
I0
Read-Only
Register 7 Temperature VS Monitor
Overcurrent
CLR7 TSD TW OV(W) UV HSB2 HSB1 LSB2 LSB1 HSA2 HSA1 LSA2 LSA1
22/40
Doc ID 11778 Rev 7
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