74HC404D 데이터 시트보기 (PDF) - Philips Electronics

부품명

상세내역

제조사

74HC404D

5-Bit x 64-word FIFO register; 3-state

Philips Electronics 

Philips Semiconductors

5-Bit x 64-word FIFO register; 3-state

With FIFO empty; SO is held HIGH in anticipation

handbook, full pagewidth

SI INPUT

2 VM (1)

Product specification

74HC/HCT7404

SO INPUT

1 VM (1)

DOR OUTPUT

Qn OUTPUT

t PLH

tW

ripple through

delay

3 VM (1)

6

5

t PHL t PLH

4

MGA669

(1) HC : VM = 50%; VI = GND to VCC.

HCT : VM = 1.3 V; VI = GND to 3 V.

Fig.11 Waveforms showing ripple through delay SI input to DOR output, DOR output pulse width and propagation

delay from the DOR pulse to the Qn output.

Notes to Fig.11

1. FIFO is initially empty, SO is held HIGH

2. SI pulse; loads data into FIFO and initiates ripple through process

3. DOR flag signals the arrival of valid data at the output stage

4. Output transition; data arrives at output stage after the specified propagation delay between the rising edge of the

DOR pulse to the Qn output

5. DOR goes LOW; data shift-out is complete, FIFO is empty again

6. SO set LOW; necessary to complete shift-out process. DOR remains LOW, because FIFO is empty.

September 1993

16

Share Link: