ISPLSI2128V-60LT100I 데이터 시트보기 (PDF) - Lattice Semiconductor
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ISPLSI2128V-60LT100I Datasheet PDF : 15 Pages
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Specifications ispLSI 2128V
Power Consumption
Power consumption in the ispLSI 2128V device depends Figure 3 shows the relationship between power and
on two primary factors: the speed at which the device is operating speed.
operating and the number of Product Terms used.
Figure 3. Typical Device Power Consumption vs fmax
275
250
ispLSI 2128V
225
200
DESIGNS
175
0
20
40
60
80
fmax (MHz)
Notes: Configuration of eight 16-bit counters
Typical current at 3.3V, 25° C
NEW
ICC can be estimated for the ispLSI 2128V using the following equation:
R ICC (mA) = 40 + (# of PTs * 0.6) + (# of nets * Max freq * 0.004)
O Where:
F # of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
E Max freq = Highest Clock Frequency to the device (in MHz)
V The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption
8 of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is
2 sensitive to operating conditions and the program in the device, the actual ICC should be verified.
1 0127/2128V
2 Power-up Considerations
SI When Lattice 3.3V 2000V devices are used in mixed 5V/
3.3V applications, some consideration needs to be given
L to the power-up sequence. When the I/O pins on the
p 3.3V ispLSI devices are driven directly by 5V devices, a
is low impedance path can exist on the 3.3V device be-
This latch-up condition occurs only during the power-up
sequence when the 5V supply comes up before the 3.3V
supply. The Lattice 3.3V ispLSI devices are guaranteed
to withstand 5V interface signals within the device oper-
ating Vcc range of 3.0V to 3.6V.
tween its I/O and Vcc pins when the 3.3V supply is not
present. This low impedance path can cause current to
E flow from the 5V device into the 3.3V ispLSI device. The
S maximum current occurs when the signals on the I/O pins
U are driven high by the 5V devices. If a large enough
The recommended power-up options are as follows:
Option 1: Ensure that the 3.3V supply is powered-up and
stable before the 5V supply is powered up.
current flows through the 3.3V I/O pins, latch-up can Option 2: Ensure that the 5V device outputs are driven to
occur and permanent device damage may result.
a high impedance or logic low state during power-up.
8
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