ISPLSI2128V-60LJ84I 데이터 시트보기 (PDF) - Lattice Semiconductor

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ISPLSI2128V-60LJ84I

3.3V High Density Programmable Logic

Lattice Semiconductor 

Specifications ispLSI 2128V

ispLSI 2128V Timing Model

I/O Cell

GRP

GLB

ORP

I/O Cell

Feedback

Ded. In

#21

Comb 4 PT Bypass #23

I/O Pin

(Input)

I/O Delay

#20

Reset

GRP

#22

#45

Reg 4 PT Bypass

#24

20 PT

XOR Delays

#25, 26, 27

GLB Reg Bypass

#28

GLB Reg

Delay

D

Q

RST

#29, 30,

31, 32

Control RE

PTs OE

ORP Bypass

#37

S ORP

Delay

DESIGN #36

#38,

39

I/O Pin

(Output)

Y0,1,2

GOE 0

#43, 44

#42

#33, 34, CK

35

NEW

#40, 41

0491/2032

Derivations of tsu, th and tco from the Product Term Clock

R tsu

= Logic + Reg su - Clock (min)

O = (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))

F = (#20+ #22+ #26) + (#29) - (#20+ #22+ #35)

5.9 ns = (0.4 + 1.2 + 9.5) + (0.2) - (0.4 + 1.2 + 3.8)

E th

8V 1.5 ns

= Clock (max) + Reg h - Logic

= (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)

= (#20+ #22+ #35) + (#30) - (#20+ #22+ #26)

= (0.4 + 1.2 + 5.6) + (5.4) - (0.4 + 1.2 + 9.5)

2 tco

= Clock (max) + Reg co + Output

1 = (tio + tgrp + tptck(max)) + (tgco) + (torp + tob)

2 = (#20+ #22+ #35) + (#31) + (#36 + #38)

I 12.4 ns = (0.4 + 1.2 + 5.6) + (1.6) + (1.4 + 2.2)

S Note: Calculations are based upon timing specifications for the ispLSI 2128V-80L.

ispL Table 2-0042/2128V

USE

7

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