ISPLSI2128V-60LT100I 데이터 시트보기 (PDF) - Lattice Semiconductor

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ISPLSI2128V-60LT100I

3.3V High Density Programmable Logic

Lattice Semiconductor 

Specifications ispLSI 2128V

Pin Description

NAME

84-PIN PLCC

PIN NUMBERS

100-PIN TQFP

PIN NUMBERS

DESCRIPTION

I/O 0 - I/O 3

I/O 4 - I/O 7

I/O 8 - I/O 11

I/O 12 - I/O 15

I/O 16 - I/O 19

I/O 20 - I/O 23

I/O 24 - I/O 27

I/O 28 - I/O 31

I/O 32 - I/O 35

I/O 36 - I/O 39

I/O 40 - I/O 43

I/O 44 - I/O 47

I/O 48 - I/O 51

I/O 52 - I/O 55

I/O 56 - I/O 59

I/O 60 - I/O 63

IN 4 - IN 7

26, 27, 28, 29,

30, 31, 32, 33,

34, 35, 36, 37,

38, 39, 40, 41,

45, 46, 47, 48,

49, 50, 51, 52,

53, 54, 55, 56,

57, 58, 59, 60,

68, 69, 70, 71,

72, 73, 74, 75,

76, 77, 78, 79,

80, 81, 82, 83,

3, 4, 5, 6,

7, 8, 9, 10,

11, 12, 13, 14,

15, 16, 17, 18

17, 18, 19, 20, Input/Output Pins - These are the general purpose I/O pins used by

22, 23, 24, 26, the logic array.

27, 28, 29, 30,

32, 33, 34, 35,

40, 41, 42, 43,

45, 46, 47, 48,

49, 51, 52, 53,

55, 56, 57, 58,

67, 68, 69, 70,

72, 73, 74, 76,

77, 78, 79, 80,

82, 83, 84, 85,

90, 91, 92, 93,

95, 96, 97, 98,

99, 1, 2, 3,

5, 6, 7, 8

66, 88, 38, 9

Dedicated input pins to the device

DESIGNS

GOE 0, GOE 1

RESET

Y0, Y1, Y2

ispEN

64, 22

20

19, 67, 62

24

62, 13

11

10, 65, 60

15

Global Output Enable input pins

Active Low (0) Reset pin which resets all the registers in the device.

W Dedicated Clock input. This clock input is connected to one of the clock

E inputs of all the GLBs in the device.

N Input — Dedicated in-system programming Boundary Scan enable input

pin. This pin is brought low to enable the programming mode. The TMS,

TDI, TDO and TCK controls become active.

R TDI/IN 0

25

16

Input — This pin performs two functions. When ispEN is logic low, it

functions as a serial data input pin to load programming data into the

device. When ispEN is high, it functions as a dedicated input pin.

O TCK/IN 3

61

59

Input — This pin performs two functions. When ispEN is logic low, it

Ffunctions as a clock pin for the ISP/Boundary Scan state machine.

When ispEN is high, it functions as a dedicated input pin.

TMS/IN 1

43

37

Input — This pin performs two functions. When ispEN is logic low, it

Efunctions as a mode control pin for the ISP/Boundary Scan state

machine. When ispEN is high, it functions as a dedicated input pin.

8V TDO/IN 2

1

87

Output/Input — This pin performs two functions. When ispEN is logic

low, it functions as an output pin to read serial shift register data. When

ispEN is high, it functions as a dedicated input pin.

12 GND

23, 44, 63, 84 14, 39, 61, 86 Ground (GND)

2 VCC

2, 21, 42, 65 12, 36, 63, 89 Vcc

SI NC1

66

4, 21, 25, 31,

44, 50, 54, 64,

71, 75, 81, 94,

100

No Connect.

ispL 1. NC pins are not to be connected to any active signal, VCC or GND.

Table 2-0002B/2128V

USE

10

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