LX128EB-5FN208I 데이터 시트보기 (PDF) - Lattice Semiconductor

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LX128EB-5FN208I

High Performance Interfacing and Switching

Lattice Semiconductor 

Lattice Semiconductor

ispGDX2 Family Data Sheet

High Speed Serial Interface Block (sysHSI Block)1

The High Speed Serial Interface (sysHSI) allows high speed serial data transfer over a pair of LVDS I/O. The

ispGDX2 devices have multiple sysHSI Blocks.

Each sysHSI Block has two SERDES blocks which contain two main sub-blocks, Transmitter (with a serializer) and

Receiver (with a deserializer) including Clock/Data Recovery Circuit (CDR). Each SERDES can be used as a full

duplex channel. The two SERDES in a given sysHSI Block share a common clock and must operate at the same

nominal frequency. Figure 14 shows the sysHSI Block.

Device features support two data coding modes: 10B/12B and 8B/10B (for use with other encoding schemes, see

Lattice’s sysHSI application notes). The encoding and decoding of the 10B/12B standard are performed within the

device in dedicated logic. For the 8B/10B standard, the symbol boundaries are aligned internally but the encoding

and decoding are performed outside the device.

Each SERDES block receives a single high speed serial data input stream (with embedded clock) from an input,

and provide a low speed 10-bit wide data stream and a recovered clock to the device. For transmitting, the SER-

DES converts a 10-bit wide low-speed data stream to a single high-speed data stream with embedded clock for

output.

Additionally, multiple sysHSI Blocks can be grouped together to form a source synchronous interface of between 1-

8 channels.

Figure 15 shows the connections of the SERDES block with the FIFO, sysIO block and the MRB. Table 6 provides

the descriptions of the SERDES.

For more information on the SERDES/CDR, refer to Lattice technical note number TN1020, sysHSI Usage Guide-

lines.

Table 6. SERDES Signal Descriptions

Signal

CDRRSTb

SYDT

CAL

RXD

TXD

REFCLK

SIN

SOUT

SS_CLKIN

SS_CLKOUT

RECCLK

CSLOCK

I/O

I

O

I

Internal

Internal

Internal

I

O

I

O

Internal

Internal

Description

Resets the CDR circuit of sysHSI block

Symbol alignment detect for sysHSI block

Initiates source synchronous calibration sequence

Parallel data in for sysHSI block

Parallel data out for sysHSI block

Reference clock received from the clock tree

Serial data input for sysHSI block (LVDS input)

Serial data output for sysHSI block (LVDS output)

Clock input for source synchronous group

Clock output for source synchronous group

Recovered clock from encoded data by CDR of sysHSI block

Lock output of the PLL associated with sysHSI block

1. “E-Series” does not support sysHSI.

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