ISL8024 데이터 시트보기 (PDF) - Intersil
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ISL8024 Datasheet PDF : 20 Pages
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ISL8023, ISL8024
Vo
R2
C3
V FB -
V COMP
R3
V REF GM
+
R6
C7
C6
FIGURE 43. TYPE II COMPENSATOR
Figure 43 shows the type II compensator and its transfer function
is expressed as Equation 14:
Av(S)=
-vˆ---cv-ˆ--oF---m-B----p- =
------G-----M---------
C6 + C7
⎝⎛---1-----+------ω--------c-S-----z------1----⎠⎞----⎝⎛--1-----+------ω---------cS------z------2----⎠⎞-
S⎝⎛1 + ω----S-c---p-⎠⎞
(EQ. 14)
where,
ωcz1
=
-------1-------
R6C6
,
ωcz2
=
-R----2--1-C-----3-, ωcp=
--C----6-----+----C-----7--
R6C6C7
Compensator design goal:
High DC gain
Loop bandwidth fc:
⎛
⎝
1--
4
t
o
1--1--0--⎠⎞
f
s
Gain margin: >10dB
Phase margin: 40°
The compensator design procedure is as follows:
Put compensator zero ωcz1=
(1
t
o
3
)
-------1-------
RoCo
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower. An
optional zero can boost the phase margin. ωCZ2 is a zero due to
R2 and C3.
Put compensator zero ωcz2=
(5
t
o
8
)
-------1-------
R2C3
The loop gain Tv(S) at crossover frequency of fc has unity gain.
Therefore, the compensator resistance R6 is determined by
Equation 15.
R6 = 2----π-G---f--Mc---V---⋅-o--V--C--F--o--B--R----t
(EQ. 15)
where GM is the sum of the trans-conductance, gm, of the
voltage error amplifier in each phase. Compensator capacitor C6
is then given by Equation 16.
C6
=
----------1----------
R6ωcz1
,
C7
=
------------1------------
2πR6fesr
(EQ. 16)
Example: VIN = 5V, Vo = 1.8V, Io = 4A, fs = 1MHz,
Co = 2X22µF/3mΩ, L = 1µH, GM = 150µs, Rt = 0.20V/A,
VFB = 0.6V, Se = 440mV/µs, Sn = 6.4×105V/s, fc = 100kHz, then
compensator resistance R6 = 100kΩ.
Put the compensator zero at 8kHz, and put the compensator pole
at either half of switching frequency or ESR zero. We choose
500kHz here, then the compensator capacitors are:
C6 = 220pF, C7 = 3pF (There is approximately 3pF parasitic
capacitance from VCOMP to GND; Therefore, C7 optional).
Figure 44 shows the simulated voltage loop gain. It is shown that
it has 90kHz loop bandwidth with 70° phase margin and 10dB
gain margin.
60
45
30
15
0
-15
-30
100
1k
10k
100k
1M
f (fi)
180
150
120
90
60
30
0
100
1k
10k
100k
1M
f (fi)
FIGURE 44. SIMULATED LOOP GAIN
18
FN7812.2
May 17, 2012
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