ISL70227SEHVF 데이터 시트보기 (PDF) - Intersil
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ISL70227SEHVF Datasheet PDF : 18 Pages
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ISL70227SEH
Ordering Information
ORDERING NUMBER
(Notes 1, 2)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
5962R1222301VXA
ISL70227SEHVF
-55 to +125
10 Ld Flatpack
K10.A
ISL70227SEHF/PROTO
ISL70227 SEHF/PROTO
-55 to +125
10 Ld Flatpack
K10.A
5962R1222301V9A
ISL70227SEHVX
-55 to +125
Die
ISL70227SEHX/SAMPLE
ISL70227SEHVX/SAMPLE
-55 to +125
Die
ISL70227MHEVAL1Z
Evaluation Board
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISL70227SEH. For more information on MSL please see techbrief TB363.
Pin Configuration
ISL70227SEH
(10 LD FLATPACK)
TOP VIEW
OUTA
-IN A
+IN A
NC
V-
1
10
2
9
3 -+
8
4
+- 7
5
6
V+
OUT B
-IN B
+IN B
NC
Pin Descriptions
PIN NUMBER
3
5
7
8
9
10
1
2
4, 6
PIN NAME
+IN A
V-
+IN B
-IN B
OUT B
V+
OUT A
-IN A
NC
EQUIVALENT CIRCUIT
Circuit 1
Circuit 3
Circuit 1
Circuit 1
Circuit 2
Circuit 3
Circuit 2
Circuit 1
-
DESCRIPTION
Amplifier A non-inverting input
Negative power supply
Amplifier B non-inverting input
Amplifier B inverting input
Amplifier B output
Positive power supply
Amplifier A output
Amplifier A inverting input
Not Connected – This pin is not electrically connected internally.
V+
IN-
IN+
V-
CIRCUIT 1
V+
OUT
V-
CIRCUIT 2
V+
CAPACITIVELY
TRIGGERED ESD
CLAMP
V-
CIRCUIT 3
2
FN7958.1
August 24, 2012
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