ISL6413 데이터 시트보기 (PDF) - Intersil

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ISL6413

Triple Output Regulator with Single Synchronous Buck and Dual LDO

Intersil 

ISL6413

Electrical Specifications

Recommended operating conditions unless

Capacitors = 33nF for LDO1 and LDO2. TA

otherwise noted.

= 25oC. (Note 2)

VIN = VIN_LDO

(Continued)

=

PVCC

=

3.3V,

Compensation

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

PGOOD Output Leakage Current

PWM OUTPUT OVER VOLTAGE

VOUT = 3.3V

-

0.01

0.1

µA

Over Voltage Threshold

28

33

38

%

NOTE:

3. Specifications at -40oC and +85oC are guaranteed by design/characterization, not production tested.

4. This is the VIN current consumed when the device is active but not switching. Does not include gate drive current.

5. The dropout voltage is defined as VIN - VOUT, when VOUT is 50mV below the value of VOUT for VIN = VOUT + 0.5V.

6. The RESET timeout period is linear with CT at the slope of 2.5ms/nF. Thus, at 10nF (0.01µF) the RESET time is 25ms; at 1000nF (0.1µF) the

RESET time would be 250ms.

7. Guaranteed by design, not production tested.

Typical Performance Curves

VIN

1V/DIV

1V/DIV

0V

1V/DIV

VOUT1

0V

0V

TIME (ms)

(2ms/DIV)

FIGURE 1. PWM SOFTSTART

TIME (µs)

(0.5µs/DIV)

FIGURE 2. PWM PHASE NODE SWITCHING

20mV/

DIV

TIME (µs)

(2µs/DIV)

FIGURE 3. PWM OUTPUT RIPPLE WAVEFORMS

1.82

1.815

1.81

1.805

1.8

0

0.05

0.1

0.15

0.2

0.25

0.3

LOAD CURRENT (A)

FIGURE 4. PWM LOAD REGULATION

6

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