IS41C16256 데이터 시트보기 (PDF) - Integrated Silicon Solution

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IS41C16256

256K x 16 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

Integrated Silicon Solution 

IS41C16256

IS41LV16256

ISSI ®

ELECTRICAL CHARACTERISTICS(1)

(Recommended Operation Conditions unless otherwise noted.)

Symbol Parameter

Test Condition

Speed Min. Max. Unit

IIL

Input Leakage Current

Any input 0V ≤ VIN ≤ Vcc

Other inputs not under test = 0V

–10 10 µA

IIO

Output Leakage Current

Output is disabled (Hi-Z)

0V ≤ VOUT ≤ Vcc

–10 10 µA

VOH

Output High Voltage Level

IOH = –2.5 mA

2.4 —

V

VOL

Output Low Voltage Level

ICC1

Stand-by Current: TTL

IOL = +2.1 mA

—

0.4

V

RAS, LCAS, UCAS ≥ VIH Commercial 5V

—

Industrial 5V —

Commercial 3V —

Industrial 3V —

3

mA

4

2

3

ICC2

Stand-by Current: CMOS

RAS, LCAS, UCAS ≥ VCC – 0.2V

5V —

3V —

2

mA

1

ICC3

Operating Current:

RAS, LCAS, UCAS,

Random Read/Write(2,3,4)

Address Cycling, tRC = tRC (min.)

Average Power Supply Current

ICC4

Operating Current:

RAS = VIL, LCAS, UCAS,

EDO Page Mode(2,3,4)

Cycling tPC = tPC (min.)

Average Power Supply Current

-35 — 230 mA

-50 — 180

-60 — 170

-35 — 220 mA

-50 — 170

-60 — 160

ICC5

Refresh Current:

RAS-Only(2,3)

RAS Cycling, LCAS, UCAS ≥ VIH

tRC = tRC (min.)

Average Power Supply Current

-35 — 230 mA

-50 — 180

-60 — 170

ICC6

Refresh Current:

RAS, LCAS, UCAS Cycling

CBR(2,3,5)

tRC = tRC (min.)

Average Power Supply Current

-35 — 230 mA

-50 — 180

-60 — 170

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device

operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.

2. Dependent on cycle rates.

3. Specified values are obtained with minimum cycle time and the output open.

4. Column-address is changed once each EDO page cycle.

5. Enables on-chip refresh and address counters.

6

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. J

06/29/00

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