CY7C024(1999) 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C024
(Rev.:1999)
(Rev.:1999)
Cypress Semiconductor
CY7C024 Datasheet PDF : 19 Pages
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CY7C024/0241
CY7C025/0251
Switching Characteristics Over the Operating Range[9] (continued)
7C024/0241–15 7C024/0241–25
7C025/0251–15 7C025/0251–25
Parameter
BUSY TIMING[15]
Description
Min. Max. Min. Max.
tBLA
BUSY LOW from Address
15
20
Match
tBHA
BUSY HIGH from Address
15
20
Mismatch
tBLC
BUSY LOW from CE LOW
15
20
tBHC
BUSY HIGH from CE HIGH
15
20
tPS
Port Set-Up for Priority
5
5
tWB
R/W HIGH after BUSY
0
0
(Slave)
tWH
tBDD[16]
R/W HIGH after BUSY
HIGH (Slave)
BUSY HIGH to Data Valid
INTERRUPT TIMING[15]
13
20
Note
16
Note
16
tINS
INT Set Time
tINR
INT Reset Time
SEMAPHORE TIMING
15
20
15
20
tSOP
SEM Flag Update Pulse (OE 10
12
or SEM)
tSWRD
SEM Flag Write to Read
5
10
Time
tSPS
SEM Flag Contention
5
10
Window
tSAA
SEM Address Access Time
15
25
Notes:
15. Test conditions used are Load 2.
16. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
7C024/0241–35
7C025/0251–35
Min. Max.
20
20
20
20
5
0
30
Note
16
25
25
15
10
10
35
7C024/0241–55
7C025/0251–55
Min. Max.
45
40
40
35
5
0
40
Note
16
30
30
20
15
15
55
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Retention Mode
Timing
The CY7C024/0241 is designed with battery backup in mind.
Data retention voltage and supply current are guaranteed over
temperature. The following rules insure data retention:
1. Chip enable (CE) must be held HIGH during data retention, with-
in VCC to VCC – 0.2V.
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (4.5 volts).
Data Retention Mode
VCC
4.5V
VCC > 2.0V
4.5V
tRC
CE
VCC to VCC – 0.2V
VIH
Parameter
Test Conditions[17]
7C024–13
Max. Unit
ICCDR1
@ VCCDR = 2V
1.5 mA
Note:
17. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not
tested.
8
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