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IDT82V3380

SYNCHRONOUS ETHERNET WAN PLL

Integrated Device Technology 

IDT82V3380

SYNCHRONOUS ETHERNET WAN PLL

Table 1: Pin Description (Continued)

Name

Pin No.

I/O

Type

Description 1

ALE: Address Latch Enable

In Multiplexed mode, the address on AD[7:0] pins is sampled into the device on the falling

edge of ALE.

ALE / SCLK

73

I

pull-down

CMOS

SCLK: Shift Clock

In Serial mode, a shift clock is input on this pin.

Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated

on the active edge of SCLK. The active edge is determined by the CLKE.

RDY

TRST

TMS

TCK

TDI

TDO

VDDD1

VDDD2

In EPROM, Intel and Motorola modes, this pin should be connected to ground.

RDY: Ready/Data Acknowledge

In Multiplexed and Intel modes, a high level on this pin indicates that a read/write cycle is

completed. A low level on this pin indicates that wait state must be inserted.

75

O

CMOS In Motorola mode, a low level on this pin indicates that valid information on the data bus is

ready for a read operation or acknowledges the acceptance of the written data during a write

operation.

In EPROM and Serial modes, this pin should be connected to ground.

JTAG (per IEEE 1149.1)

2

I

pull-down

CMOS

TRST: JTAG Test Reset (Active Low)

A low signal on this pin resets the JTAG test port.

This pin should be connected to ground when JTAG is not used.

7

I

pull-up

CMOS

TMS: JTAG Test Mode Select

The signal on this pin controls the JTAG test performance and is sampled on the rising edge

of TCK.

TCK: JTAG Test Clock

9

I

pull-down

CMOS

The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge

of TCK and TDO is updated on the falling edge of TCK.

If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely

retain their state.

23

I

pull-up

CMOS

TDI: JTAG Test Data Input

The test data is input on this pin. It is clocked into the device on the rising edge of TCK.

TDO: JTAG Test Data Output

The test data is output on this pin. It is clocked out of the device on the falling edge of TCK.

21

O

CMOS TDO pin outputs a high impedance signal except during the process of data scanning.

This pin can indicate the interrupt of T0 selected input clock fail, as determined by the

LOS_FLAG_ON_TDO bit (b6, 0BH). Refer to Chapter 3.8.1 Input Clock Validity for details.

Power & Ground

12

VDDDn: 3.3 V Digital Power Supply

Each VDDDn should be paralleled with ground through a 0.1 µF capacitor.

16

VDDD3

13

VDDD4

50

Power

-

VDDD5

61

VDDD6

85

VDDD7

86

Pin Description

17

May 19, 2009

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