IDT72V36104 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT72V36104

3.3 VOLT CMOS SyncBiFIFO™ WITH BUS-MATCHING

Integrated Device Technology 

IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFOTM WITH

BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2

CLKA

1

2

3

4

CLKB

1

2

3

4

COMMERCIAL TEMPERATURE RANGE

ENB LOW

tRSTS

RT1

tRTMS

tRSTH

tRTMH

RTM

ORB

(2)

tREF

(2)

tREF

tA

B0-Bn

Wx

W1

4664 drw 33

NOTES:

1. CSB = LOW

2. Retransmit setup is complete after ORB returns HIGH, only then can a read operation begin.

3. W1 = first word written to the FIFO1 after Master Reset on FIFO1.

4. No more than D-2 may be written to the FIFO1 between Reset of FIFO1 (Master or Partial) and Retransmit setup. Therefore, IRA will be LOW throughout the Retransmit

setup procedure. D = 16,385, 32,769 and 65,537 for the IDT72V3684, IDT72V3694 and IDT72V36104 respectively.

Figure 31. Retransmit Timing for FIFO1 (FWFT Mode)

CLKB

CLKA

1

2

3

4

1

2

3

4

ENA LOW

tRSTS

RT2

tRTMS

tRSTH

tRTMH

RTM

ORA

(2)

tREF

(2)

tREF

tA

A0-An

Wx

W1

4677 drw34

NOTES:

1. CSA = LOW

2. Retransmit setup is complete after ORA returns HIGH, only then can a read operation begin.

3. W1 = first word written to the FIFO2 after Master Reset on FIFO2.

4. No more than D-2 may be written to the FIFO2 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore, IRB will be LOW throughout the Retransmit

setup procedure. D = 16,385, 32,769 and 65,537 for the IDT72V3684, IDT72V3694 and IDT72V36104 respectively.

Figure 32. Retransmit Timing for FIFO2 (FWFT Mode)

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