IDT72V3641 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT72V3641

3.3 VOLT CMOS SyncFIFO™ 512 x 36 1,024 x 36 2,048 x 36

Integrated Device Technology 

IDT72V3631/72V3641/72V3651

3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36

CLKA

(1)

tSKEW1

1

IR

FIFO Filled to First Restransmit Word

COMMERCIAL TEMPERATURE RANGE

2

tPIR

One or More Write Locations Available

CLKB

tRMS

tRMH

RTM

4658 drw 16

NOTE:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising

CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.

Figure 13. IR Timing from the End of Retransmit Mode when One or More Write Locations are Available

CLKA

AF

(1)

tSKEW2

1

(Depth(2)-Y) or More Words Past First Restransmit Word

2

tPAE

(Y+1) or More Write Locations Available

CLKB

tRMS

tRMH

RTM

NOTES:

4658 drw 17

1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising

CLKA edge is less than tSKEW2, then AF may transition HIGH one CLKA cycle later than shown.

2. Depth is 512 for the IDT72V3631, 1,024 for the IDT72V3641, and 2,048 for the IDT72V3651.

3. Y is the value loaded in the Almost-Full flag Offset register.

Figure 14. AF Timing from the End of Retransmit Mode when (Y+1) or More Write Locations are Available

CLKA

CSA

W/RA

MBA

ENA

A0 - A35

CLKB

MBF1

CSB

W/RB

MBB

ENB

B0 - B35

tENS2

tENS2

tENS2

tENS2

tDS

W1

tENH2

tENH2

tENH2

tENH2

tDH

tPMF

tPMF

tENS1

tENH1

tEN

tPMR

tMDV

tDIS

FIFO Output Register

W1 (Remains valid in Mail1 Register after read)

4658 drw 18

Figure 15. Timing for Mail1 Register and MBF1 Flag

18

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