IDT72V801L20PFGI8(2014) 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT72V801L20PFGI8 Datasheet PDF : 16 Pages
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IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tRS
RSA (RSB)
RENA1, RENA2
(RENB1, RENB2)
tRSS
tRSR
WENA1
(WENB1)
WENA2/LDA(1)
(WENB2/LDB)
tRSS
tRSS
tRSR
tRSR
tRSF
EFA, PAEA
(EFB, PAEB)
tRSF
FFA, PAFA
(FFA, PAFA)
QA0 - QA8
tRSF
OEA (OEB) = 1(2)
(QB0 - QB8)
OEA (OEB) = 0
4093 drw 06
NOTES:
1. Holding WENA2/LDA (WENB2/LDB) HIGH during reset will make the pin act as a second Write Enable pin. Holding WENA2/LDA (WENB2/LDB) LOW during reset will make
the pin act as a load enable for the programmable flag offset registers.
2. After reset, QA0 - QA8 (QB0 - QB8) will be LOW if OEA (OEB) = 0 and tri-state if OEA (OEB) = 1.
3. The clocks RCLKA, WCLKA (RCLKB, WCLKB) can be free-running during reset.
Figure 4. Reset Timing
WCLKA (WCLKB)
(DA0 - DA8
DB0 - DB8)
WENA1
(WENB1)
WENA2 (WENB2)
(If Applicable)
FFA
(FFB)
tSKEW1(1)
RCLKA (RCLKB)
tCLKH
tCLK
tCLKL
tDS
DATA IN VALID
tENS
tENS
tWFF
tDH
tENH
tENH
tWFF
NO OPERATION
NO OPERATION
RENA1, RENA2
(RENB1, RENB2)
4093 drw 07
NOTE:
1. tSKEW1 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for FFA (FFB) to change during the current clock cycle. If the time
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then FFA (FFB) may not change state until the next WCLKA (WCLKB)
edge.
Figure 5. Write Cycle Timing
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