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IDT72801L35PF

DUAL CMOS SyncFIFO™

Integrated Device Technology 

72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO™

256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

WCLKA

(WCLKB)

tDS

DA0 - DA8

(DB0 - DB8)

WENA1

tENS

(WENB1)

D1

D0 (First Valid

WENA2 (WENB2)

(If Applicable)

RCLKA

(RCLKB)

EFA (EFB)

tSKEW1

tFRL(1)

tREF

COMMERCIAL TEMPERATURE

D2

D3

RENA1, RENA2

(RENB1, RENB2)

QA0 - QA8

(QB0 - QB8)

OEA (OEB)

tA

tOLZ

tOE

NOTE:

1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1

When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1

The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).

Figure 7. First Data Word Latency Timing

tA

D0

D1

3034 drw 09

5.15

12

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