IDT72201L10(2017) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT72201L10
(Rev.:2017)

CMOS SyncFIFO™ 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

Integrated Device Technology 

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

WCLK

LD

WEN1

D0 - D7

tCLK

tCLKH

tCLKL

tENS

tENS

tDS

PAE OFFSET

(LSB)

tENH

tDH

PAE OFFSET

(MSB)

PAF OFFSET

(LSB)

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PAF OFFSET

(MSB)

2655 drw 14

Figure 12. Write Offset Registers Timing

RCLK

LD

REN1,

REN2

tCLK

tCLKH

tCLKL

tENS

tENS

Q0 - Q7 DATA IN OUTPUT REGISTER

tENH

tA

EMPTY OFFSET

(LSB)

EMPTY OFFSET

(MSB)

Figure 13. Read Offset Registers Timing

©

12

FULL OFFSET

(LSB)

FULL OFFSET

(MSB)

2655 drw15

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