IDT71V428YS10YG 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT71V428YS10YG

3.3V CMOS Static RAM 4 Meg (1M x 4-Bit)

Integrated Device Technology 

IDT71V428S, IDT71V428L, 3.3V CMOS Static RAM

4 Meg (1M x 4-Bit)

Commercial and Industrial Temperature Ranges

Timing Waveform of Write Cycle No.1 (WE Controlled Timing)(1,2,4)

ADDRESS

CS

WE

DATAOUT

DATAIN

tWC

tAW

tAS

tWP(2)

tWR

tWHZ (5)

tOW (5)

(3)

HIGH IMPEDANCE

tDH

tDW

DATAIN VALID

tCHZ (5)

(3)

3623 drw 08

Timing Waveform of Write Cycle No.2 (CS Controlled Timing)(1,4)

ADDRESS

CS

tAS

WE

DATAIN

tWC

tAW

tCW

tWR

tDW

tDH

DATAIN VALID

3623 drw 09

NOTES:

1. A write occurs during the overlap of a LOW CS and a LOW WE.

2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to

be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as

the specified tWP.

3. During this period, I/O pins are in the output state, and input signals must not be applied.

4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

5. Transition is measured ±200mV from steady state.

6.742

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