IDT71V421L 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT71V421L Datasheet PDF : 14 Pages
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IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
71V321X25
71V421X25
Com'l
& Ind
71V321X35
71V421X35
Com'l Only
71V321X55
71V421X55
Com'l Only
Symbol
Parameter
BUSY Timing (For Master IDT71V321 Only)
tBAA
BUSY Access Time from Address
tBDA
BUSY Disable Time from Address
tBAC
BUSY Access Time from Chip Enable
tBDC
BUSY Disable Time from Chip Enable
tWH
Write Hold After BUSY(5)
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
tAPS
Arbitration Priority Set-up Time(2)
tBDD
BUSY Disable to Valid Data(3)
BUSY Timing (For Slave IDT71V421 Only)
tWB
BUSY Input to Write(4)
tWH
Write Hold After BUSY(5)
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
Min.
Max.
Min.
Max.
Min.
Max.
____
20
____
20
____
30
____
20
____
20
____
30
____
20
____
20
____
30
____
20
____
20
____
30
12
____
15
____
20
____
____
50
____
60
____
80
____
35
____
45
____
65
5
____
5
____
5
____
____
30
____
30
____
45
0
____
0
____
0
____
12
____
15
____
20
____
____
50
____
60
____
80
____
35
____
45
____
65
NOTES:
1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY."
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3026 tbl 11
Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)
ADDR"A"
tWC
MATCH
tWP
R/W"A"
DATAIN "A"
tAPS(1)
tDW
tDH
VALID
ADDR"B"
BUSY"B"
tBAA
MATCH
tBDA
tBDD
tWDD
DATAOUT"B"
NOTES:
tDDD
1. To ensure that the earlier of the two ports wins. tAPS is ignored for SLAVE (71V421).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
6.942
VALID
3026 drw 10
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