IDT71V421L 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT71V421L

HIGH SPEED 3.3V 2K X 8 DUAL-PORT STATIC RAM WITH INTERRUPTS

Integrated Device Technology 

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts

Timing Waveform of Write with BUSY(4)

tWP

R/W"A"

BUSY"B"

tWB(3)

R/W"B"

(2)

Industrial and Commercial Temperature Ranges

tWH (1)

,

NOTES:

3026 drw 11

1. tWH must be met for both BUSY input (71V421, slave) or output (71V321, master).

2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes HIGH.

3. tWB is for the slave version (71V421).

4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A".

Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)

ADDR

"A" AND "B"

ADDRESSES MATCH

CE"B"

CE"A"

BUSY"A"

tAPS(2)

tBAC

tBDC

3026 drw 12

Timing Waveform of BUSY Arbritration Controlled

by Address Match Timing(1)

ADDR"A"

ADDR"B"

tAPS (2)

tRC OR tWC

ADDRESSES MATCH

ADDRESSES DO NOT MATCH

BUSY"B"

tBAA

tBDA

3026 drw 13

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (71V321 only).

61.402

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