IDT70V35S20G 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT70V35S20G

HIGH-SPEED 3.3V STATIC RAM

Integrated Device Technology 

IDT70V35/34S/L (IDT70V25/24S/L)

High-Speed 3.3V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM

Timing Waveform of Write with BUSY

tWP

R/W"A"

BUSY"B"

tWB(3)

Industrial and Commercial Temperature Ranges

tWH(1)

R/W"B"

(2)

NOTES:

1. tWH must be met for both master BUSY input (slave) and output (master).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. tWB is only for the slave version.

5624 drw 14 ,

Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)

ADDR"A"

and "B"

ADDRESSES MATCH

CE"A"

CE"B"

BUSY"B"

tAPS(2)

tBAC

tBDC

5624 drw 15

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing(1) (M/S = VIH)

ADDR"A"

ADDR"B"

BUSY"B"

tAPS (2)

ADDRESS "N"

MATCHING ADDRESS "N"

tBAA

tBDA

5624 drw 16

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

6.1482

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