IDT70V16S 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT70V16S

HIGH-SPEED 3.3V 16/8K X 9 DUAL-PORT STATIC RAM

Integrated Device Technology 

PRELIMINARYPRE

IDT70V16/5S/L

High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM

PRELIMINARY

Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side(1)

tSAA

A0-A2

SEM

I/O

VALID ADDRESS

tAW

tWR

tEW

tDW

DATAIN

VALID

tAS

tWP

tDH

VALID ADDRESS

tACE

tSOP

tOH

DATAOUT

VALID(2)

R/W

tSWRD

tAOE

OE

Write Cycle

NOTES:

1. CE = VIH for the duration of the above timing (both write and read cycle).

2. “DATAOUT VALID” represents all I/O's (I/O0-I/O8) equal to the semaphore value.

Read Cycle

5669 drw 10

Timing Waveform of Semaphore Write Condition(1,3,4)

A0"A"-A2 "A"

MATCH

SIDE(2) "A"

R/W"A"

SEM"A"

A0"B"-A2 "B"

SIDE(2) "B"

R/W"B"

tSPS

MATCH

SEM"B"

5669 drw 11

NOTES:

1. DOR = DOL =VIH, CER = CEL =VIH.

2. All timing is the same for left and right ports. Port“A” may be either left or right port. “B” is the opposite port from “A”.

3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.

4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.

6.1402

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