IDT7006L35G 데이터 시트보기 (PDF) - Integrated Device Technology

부품명

상세내역

제조사

IDT7006L35G

HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7006S/L

HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)

IDT7006X15

Com'l. Only

Symbol

Parameter

Min. Max.

BUSY TIMING (M/S = VIH)

tBAA

BUSY Access Time from Address Match

— 15

tBDA

BUSY Disable Time from Address Not Matched — 15

tBAC

BUSY Access Time from Chip Enable Low

— 15

tBDC

BUSY Disable Time from Chip Enable High

— 15

tAPS

Arbitration Priority Set-up Time(2)

5—

tBDD

BUSY Disable to Valid Data(3

— 18

tWH

Write Hold After BUSY(5)

12 —

BUSY TIMING (M/S = VIL)

tWB

BUSY Input to Write(4)

0—

tWH

Write Hold After BUSY(5)

12 —

IDT7006X17

Com'l. Only

Min. Max.

—

17

—

17

—

17

—

17

5

—

—

18

13

—

0—

13 —

PORT-TO-PORT DELAY TIMING

tWDD

Write Pulse to Data Delay(1)

tDDD

Write Data Valid to Read Data Delay(1)

— 30 — 30

— 25 — 25

IDT7006X20

Min. Max.

—

20

—

20

—

20

—

17

5

—

—

30

15

—

0

—

15

—

—

45

—

35

IDT7006X25

Min. Max. Unit

—

20 ns

—

20 ns

—

20 ns

—

17 ns

5

— ns

—

35 ns

17

— ns

0

— ns

17

— ns

—

50 ns

—

35 ns

Symbol

Parameter

BUSY TIMING (M/S = VIH)

tBAA

BUSY Access Time from Address Match

tBDA

BUSY Disable Time from Address Not Matched

tBAC

BUSY Access Time from Chip Enable Low

tBDC

BUSY Disable Time from Chip Enable High

tAPS

Arbitration Priority Set-up Time(2)

tBDD

BUSY Disable to Valid Data(3)

tWH

Write Hold After BUSY(5)

BUSY TIMING (M/S = VIL)

tWB

BUSY Input to Write(4)

tWH

Write Hold After BUSY(5)

IDT7006X35

Min. Max.

IDT7006X55

Min. Max.

IDT7006X70

Mil. Only

Min. Max. Unit

—

20

—

45

—

45 ns

—

20

—

40

—

40 ns

—

20

—

40

—

40 ns

—

20

—

35

—

35 ns

5

—

5

—

5

— ns

—

35

—

40

—

45 ns

25

—

25

—

25

— ns

0

—

0

—

0

— ns

25

—

25

—

25

— ns

PORT-TO-PORT DELAY TIMING

tWDD

Write Pulse to Data Delay(1)

tDDD

Write Data Valid to Read Data Delay(1)

—

60

—

80

—

95 ns

—

45

—

65

—

80 ns

NOTES:

2739 tbl 15

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY".

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited with port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention with port "A".

6. "X" is part numbers indicates power rating (S or L).

6.07

12

Share Link: