ICS671-06 데이터 시트보기 (PDF) - Integrated Circuit Systems
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ICS671-06 Datasheet PDF : 6 Pages
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ICS671-06
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
Parameter
Output High Voltage
Output Low Voltage
Output High Voltage,
CMOS level
Operating Supply Current
Power Down Supply
Current
Short Circuit Current
Input Capacitance
Symbol
Conditions
VOH
VOL
VOH
IOH = -12 mA
IOL = 12 mA
IOH = -12 mA
Min.
2.4
Typ.
VDD-0.4
IDD No Load, S2 = 1, S1 = 1,
Note 1
IDD CLKIN = 0, S2 = 0, S1 = 1
12
CLKIN = 0, Note 2
12
IOS Each output
±50
CIN S2, S1, FBIN
5
Max.
0.4
Units
V
V
V
35 mA
µA
µA
mA
pF
AC Electrical Characteristics
VDD = 3.3 V ±5%, Ambient Temperature -40 to +85°C, CLOAD at CLK = 15 pF, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Input Clock Frequency
Output Clock Frequency
fIN
See table on page 2
See table on page 2
10
133 MHz
10
133 MHz
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Device to Device Skew
tOR 0.8 to 2.0 V, CL = 30 pF
tOF 2.0 to 0.8 V, CL = 30 pF
tDC Measured at VDD/2
Rising edges at VDD/2
2.5 ns
2.5 ns
45
50 55
%
700 ps
Output to Output Skew
Rising edges at VDD/2
200 ps
Input to Output Skew
Rising edges at VDD/2, FBIN to
CLKA4, S1 = 1, S0 = 1, Note 1
±250 ps
Maximum Absolute JItter
130 200 ps
Cycle to Cycle Jitter
30 pF, measured at 66.67M
200 ps
15 pF, measured at 66.67M
200 ps
15 pF, measured at 133.33M
100 ps
PLL Lock Time
Note 3
1.0 ms
Note 1: With CLKIN = 100MHz, FBIN to CLKA4, all outputs at 100 MHz.
Note 2: When there is no clock signal present at CLKIN, the ICS671-06 will enter power down mode. The
PLL is stopped and the outputs are tri-state.
Note 3: With VDD at a steady rate and valid clocks at CLKIN and FBIN.
MDS 671-06 D
4
Revision 050405
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l www.icst.com
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