HT6576A 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT6576A

Advanced SCSI CHIP

Holtek Semiconductor 

HT6576A

• BIT 4: ENABLE PARITY INTERRUPT

When set, this bit causes the IRQ signal to be asserted if a parity error is detected.

• BIT 3: ENABLE EOP INTERRUPT

When set, this bit causes the IRQ signal to be asserted if EOP is received from the DMA controller.

• BIT 2: MONITOR BUSY

When set, this bit causes the IRQ signa asserted when BSY changes to the inactive state for at

least a bus settle delay.

• BIT 1: DMA MODE

• BIT 0: Arbitrate

When set, this bit starts the arbitration process.

Address 3: Target command register

7

6

5

4

LAST BYTE

X

X

X

3

ASSERT

REQ

2

ASSERT

MSG

1

ASSERT

C/D

0

ASSERT

I/O

R

R/W

R/W

R/W

R/W

• BIT 7: LAST BYTE SEND (READ ONLY)

• BIT 3: ASSERT REQ

WHEN SET, THE REQ SIGNAL IS ASSERTED ON THE SCSI BUS (IN TARGET MODE)

• BIT 2: ASSERT MSG

WHEN SET, THE MSG SIGNAL IS ASSERTED ON THE SCSI BUS (IN TARGET MODE)

• BIT 1: ASSERT C/D

WHEN SET, THE C/D SIGNAL IS ASSERTED ON THE SCSI BUS (IN TARGET MODE)

• BIT 0: ASSERT I/O

WHEN SET, THE I/O SIGNAL IS ASSERTED ON THE SCSI BUS (IN TAGRTE MODE)

Address 4: Current SCSI Bus Register

READ

7

6

5

4

3

2

1

0

RST

BSY

REQ

MSG

C/D

I/O

SEL

DBP

WRITE

7

SID7

–SELECT ENABLE REGISTER

6

5

4

SID6

SID5

SID4

3

SID3

2

SID2

1

SID1

0

SID0

5

14th July ’97

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