DS1250ABP 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS1250ABP Datasheet PDF : 10 Pages
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DC TEST CONDITIONS
Outputs Open
Cycle = 200 ns for operating current
All voltages are referenced to ground
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0 - 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input pulse Rise and Fall Times: 5 ns
DS1250Y/AB
ORDERING INFORMATION
PART
TEMP RANGE
SUPPLY
TOLERANCE
DS1250AB-70+
0°C to +70°C
5V ± 5%
DS1250ABP-70+
0°C to +70°C
5V ± 5%
DS1250AB-70IND+
-40°C to +85°C
5V ± 5%
DS1250ABP-70IND+ -40°C to +85°C
5V ± 5%
DS1250Y-70+
0°C to +70°C
5V ± 10%
DS1250YP-70+
0°C to +70°C
5V ± 10%
DS1250Y-70IND+
-40°C to +85°C 5V ± 10%
DS1250YP-70IND+
-40°C to +85°C 5V ± 10%
+Denotes a lead(Pb)-free/RoHS-compliant package.
*DS9034PC+ or DS9034PCI+ (PowerCap) required. Must be ordered separately.
PIN-PACKAGE
32 740 EDIP
34 PowerCap*
32 740 EDIP
34 PowerCap*
32 740 EDIP
34 PowerCap*
32 740 EDIP
34 PowerCap*
SPEED GRADE
(ns)
70
70
70
70
70
70
70
70
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix
character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO. LAND PATTERN NO.
32 EDIP
MDT32+6
21-0245
—
34 PCAP
PC2+5
21-0246
—
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