Philips Semiconductors
256-bit, 1-bit per word random access memories
APPLICATION INFORMATION
Extension of memory capacity
The memory capacity of the HEF4720B; V is 256 bits (or
256 words of 1 bit). The capacity of a system can be
extended in various ways by the connection of further
HEF4720B; V ICs.
Extending the word length
By connecting a number of HEF4720B; V ICs as shown in
Fig.6, the word length (i.e. bits per word) is multiplied by
that number. That is, each device stores 1 bit per word but
the total number of words remains 256. For example, if
four devices are used in this way, 256 four-binary-bit words
can be stored.
Extending the number of words
If a number of HEF4720B; V ICs are connected as shown
in Fig.7, the words available are multiplied by that number,
but the word length remains 1 bit. Notice that in this case
additional addresses are used in conjunction with the
CS input. In the case shown in Fig.7 (4 × HEF4720B; V in
parallel), the addresses and data inputs are loaded with
four inputs (= 20 pF), the CS inputs are loaded with one
input each.
Extending both the word length and number of words
Figure 8 shows how a combination of the extensions
described above can be used to obtain both greater word
length and additional words. It is clear that the capacitive
load of the driving circuits puts a limit to the free choice of
the interface. In Fig.8, each address is loaded with 16
inputs, i.e. 16 × 5 = 80 pF: each CS inverter is loaded with
8 inputs, i.e. 8 × 5 = 40 pF. The data inverters in this case
are loaded with only two inputs each.
Product specification
HEF4720B
HEF4720V
January 1995
9