
Philips Semiconductors
Programmable 4-bit binary down counter
SINGLE STAGE OPERATION
Divide-by-n; MR = LOW; CF = HIGH; CP1 = LOW
PL P3 P2 P1
P0
DIVIDE TC OUTPUT
BY PULSE WIDTH
L XX X
X
TC H H H H
TC H H H
L
TC H H L
H
TC H H L
L
TC H L H H
TC H L H
L
TC H L L
H
TC H L L
L
TC L H H H
TC L H H
L
TC L H L
H
TC L H L
L
TC L L H H
TC L L H
L
TC L L L
H
TC L L L
L
16
one clock
period
15
14
13
12
11
10
9
8
clock pulse
HIGH
7
6
5
4
3
2
1
no operation
Product specification
HEF4526B
MSI
January 1995
Fig.3 State diagram.
4