HDM8515 데이터 시트보기 (PDF) - Hynix Semiconductor

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HDM8515

DVB/DSS Compliant Receiver

Hynix Semiconductor 

1B

1C,1D

1E

1F

23

24, 25

64

FEC Lock

Bit 0. Viterbi Node Sync

When this bit is set to one, the Viterbi decoder has successfully

established node synchronization.

Bit 1. Frame Sync

When this bit is set to one, the FEC chip has successfully established

word sync and frame sync.

Bit 2. Viterbi Byte Sync

When this bit is set to one, the Viterbi decoder has successfully

established byte-synchronization.

Bit 3. Pi Ambiguity

When this bit is set to one, the Viterbi decoder has successfully

resolved pi ambiguity in the input data. (i.e inverted data)

Bit 4. Pi/2 Ambiguity

When this bit is set to one, the Viterbi decoder has successfully

resolved pi/2 ambiguity in the input data

Accumulated Reed Solomon Errors

These two registers present a count of corrected errors since it was last

reset. Bit 7 of address 1C is the MSB and bit 0 of address 1D is the

LSB. These registers are reset by writing value to address 10H.

Accumulated Reed Solomon Data

This register presents a count of the uncorrected code words since it

was last reset. When it reaches its maximum count(255), it rolls back

to zero

and starts counting again. This register is reset by writing value to

address 10H.

Device Identifier

This register present device identifier. The current value of this register

is

F0H

Reference Divider Test Output

Internal used Only.

Feedback Divider Test Output

Internal used Only.

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