6.3.2 Bus Specifications ............................................................................................... 127
6.3.3 Memory Interfaces............................................................................................... 128
6.3.4 Chip Select Signals .............................................................................................. 129
6.3.5 Address Output Method....................................................................................... 130
6.4 Basic Bus Interface ........................................................................................................... 131
6.4.1 Overview.............................................................................................................. 131
6.4.2 Data Size and Data Alignment............................................................................. 131
6.4.3 Valid Strobes ....................................................................................................... 132
6.4.4 Memory Areas ..................................................................................................... 133
6.4.5 Basic Bus Control Signal Timing ........................................................................ 134
6.4.6 Wait Control ........................................................................................................ 141
6.5 Idle Cycle.......................................................................................................................... 143
6.5.1 Operation ............................................................................................................. 143
6.5.2 Pin States in Idle Cycle........................................................................................ 146
6.6 Bus Arbiter ....................................................................................................................... 146
6.6.1 Operation ............................................................................................................. 147
6.7 Register and Pin Input Timing.......................................................................................... 149
6.7.1 Register Write Timing ......................................................................................... 149
6.7.2 BREQ Pin Input Timing ...................................................................................... 150
Section 7 I/O Ports .............................................................................................................. 151
7.1 Overview........................................................................................................................... 151
7.2 Port 1................................................................................................................................. 155
7.2.1 Overview.............................................................................................................. 155
7.2.2 Register Descriptions........................................................................................... 156
7.3 Port 2................................................................................................................................. 158
7.3.1 Overview.............................................................................................................. 158
7.3.2 Register Descriptions........................................................................................... 159
7.4 Port 3................................................................................................................................. 162
7.4.1 Overview.............................................................................................................. 162
7.4.2 Register Descriptions........................................................................................... 162
7.5 Port 4................................................................................................................................. 164
7.5.1 Overview.............................................................................................................. 164
7.5.2 Register Descriptions........................................................................................... 165
7.6 Port 5................................................................................................................................. 167
7.6.1 Overview.............................................................................................................. 167
7.6.2 Register Descriptions........................................................................................... 168
7.7 Port 6................................................................................................................................. 171
7.7.1 Overview.............................................................................................................. 171
7.7.2 Register Descriptions........................................................................................... 172
7.8 Port 7................................................................................................................................. 175
Rev. 2.00 Sep 20, 2005 page xii of xxxviii