HD64570 데이터 시트보기 (PDF) - Hitachi -> Renesas Electronics

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HD64570

Serial Communications Adaptor

Hitachi -> Renesas Electronics 

CPB (8)

DAR

(24)

BAR

SAR (24)

Reserved

CDA (16)

EDA (16)

BFL (16)*

BCR (16)

Address bus/data bus

FCT

DSR

DIR

DMR

DCR

DAR: Destination address register

BAR: Buffer address register

SAR: Source address register

CPB: Chain pointer base

CDA: Current descriptor address register

EDA: Error descriptor address register

BFL: Receive buffer length

BCR: Byte count register

FCT: End-of-frame interrupt counter

DSR: DMA status register

DIR: DMA interrupt enable register

DMR: DMA mode register

DCR: DMA command register

Request and

priority control

DMA request

signal

Comparator (16)

Incrementer/

decrementer (24)

DMA execution

control

* Channels 0 and 2 only

Bus control signals

Interrupt request signals

Single-address transfer control signal

(to MSCI)

Numbers in parentheses are

numbers of bits.

Figure 1.3 DMAC Block Diagram (one channel)

Rev. 0, 07/98, page 6 of 453

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