GS8160Z18T-225I 데이터 시트보기 (PDF) - Giga Semiconductor
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GS8160Z18T-225I Datasheet PDF : 24 Pages
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100-Pin TQFP
Commercial Temp
Industrial Temp
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
16Mb Pipelined and Flow Through 225 MHz–133 MHz
Synchronous NBT SRAM
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
Functional Description
• NBT (No Bus Turn Around) functionality allows zero wait
The GS8160Z18/36T is a 16Mbit Synchronous Static SRAM.
read-write-read bus utilization; Fully pin-compatible with
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
both pipelined and flow through NtRAM™, NoBL™ and
pipelined read/double late write or flow through read/single
ZBT™ SRAMs
late write SRAMs, allow utilization of all available bus
• 2.5 V or 3.3 V +10%/–5% core power supply
bandwidth by eliminating the need to insert deselect cycles
• 2.5 V or 3.3 V I/O supply
when the device is switched from read to write cycles.
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
-225 -200 -180 -166 -150 -133 Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.5 3.0 3.2 3.5 3.8 4.0 ns
4.4 5.0 5.5 6.0 6.6 7.5 ns
3.3 V
Pwr (x18) 840 760 695 665 610 545 mW
Pwr (x32/36) 990 895 830 760 710 630 mW
2.5 V
Pwr (x18) 625 575 525 490 450 415 mW
Pwr (x32/36) 740 665 615 565 525 465 mW
Flow
Through
2-1-1-1
tKQ
tCycle
7.0 7.5 8 8.5 10 11 ns
8.5 10 10 10 10 15 ns
3.3 V
Pwr (x18) 495 445 445 445 445 330 mW
Pwr (x32/36) 580 495 495 495 495 365 mW
2.5 V
Pwr (x18) 375 340 340 340 340 240 mW
Pwr (x32/36) 425 375 375 375 375 275 mW
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8160Z18/36T may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, meaning that in addition to the rising edge
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8160Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
Standard 100-pin TQFP package.
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock
Address
A
B
C
D
E
F
Read/Write
R
W
R
W
R
W
Flow Through
Data I/O
Pipelined
Data I/O
QA
DB
QC
DD
QE
QA
DB
QC
DD
QE
Rev: 2.10 3/2001
1/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
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