Table 1-1: Pin Descriptions (Continued)
Pin
Number
37, 64
38, 39,
42-48, 50
40, 49, 60
41, 53, 61
Name
CORE_VDD
DOUT[0:9]
IO_GND
IO_VDD
Timing
Type Description
–
Power Power supply connection for the digital core logic. Connect to +1.8V
DC digital.
Synchronous
with PCLK
Output
PARALLEL DATA BUS
Signal levels are LVCMOS/LVTTL compatible.
DOUT9 is the MSB and DOUT0 is the LSB.
HD 20-bit mode
SD/HD = LOW
20bit/10bit = HIGH
Chroma data output in SMPTE mode
SMPTE_BYPASS =HIGH
DVB_ASI = LOW
Data output in Data-Through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
HD 10-bit mode
SD/HD = LOW
20bit/10bit = LOW
Forced LOW in all modes.
SD 20-bit mode
SD/HD = HIGH
20bit/10bit = HIGH
Chroma data output in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data output in Data-Through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
Forced LOW in DVB-ASI mode
SMPTE_BYPASS = LOW
DVB_ASI = HIGH
SD 10-bit mode
SD/HD = HIGH
20bit/10bit = LOW
Forced LOW in all modes.
–
Power Ground connection for digital I/O buffers. Connect to digital GND.
–
Power Power supply connection for digital I/O buffers. Connect to +3.3V DC
digital.
GS1560A/GS1561 HD-LINX® II Dual-Rate Deserializer
Data Sheet
27360 - 12
June 2009
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