GF9105A 데이터 시트보기 (PDF) - Unspecified

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GF9105A

Component Digital Transcoder

Unspecified 

SWITCHING CHARACTERISTICS

Conditions: VDD = 5 V, TA = 0° to 70° C unless otherwise shown.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Clock Cycle Time

tCY

Non-Multiplexed Input Data AND Non-

55

-

Multiplexed Output Data LOWF=1

-

ns

All Input/Output Data Formats Except

27

-

Single Link

-

ns

SMPTE RP174 Single Link Input OR

18

-

Output Data

-

ns

Clock Pulse Width Low

tPWL

As a percentage of Min. Clock Cycle

40

-

60

%

Time

Clock Pulse Width High

tPWH

As a percentage of Min. Clock Cycle

40

-

60

%

Time

Device Latency1

Low Frequency Mode (LOWF = 1)

Dual link input and output data

34

34

34

clks

68

68

68

clks

Single link input or output data

136

136

136

clks

Note 1: Latency is defined as the number of clock cycles between the time when the data is latched into the device and when the

corresponding output data is clocked out of the device. Refer to Figure 13.

521 - 88 - 03

36

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